Microprocessor systems Lecture notes

what are microprocessor based systems and microprocessor systems and interfacing mcqs. and how a microprocessor system works pdf free download
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UNIVERSITY OF WATERLOO Department of Electrical and Computer Engineering UNIVERSITY OF WATERLOO Department of Electrical and Computer Engineering ECE 324 and ECE 325 Microprocessor Systems and Interfacing Lecture Notes Part I Section I: Course Introduction Wayne M. Loucks, PEng wmlouckspads.uwaterloo.ca Robert B. Gorbet, PEng rbgorbetuwaterloo.ca CarolC.W.Hulls,PEng chullskingcong.uwaterloo.ca January 2002 Bill Bishop, wdbishoppads.uwaterloo.ca January 2002 Copyright (c) 2002 by the University of Waterloo. All Rights Reserved.Course Introduction Course Introduction Players Course Components and Marking Scheme The graded work in the course consists of three labs, a midterm examination, and a final examination. Laboratory Instructors If the grade computed according to scheme 1 is less than 50%, then that is Roger Sanderson E22355 Ext. 6184 rsandersece.uwaterloo.ca the grade assigned. If it is greater than (or equal to) 50%, then the grade Eric Praetzel E22357 Ext. 5249 praetzelece.uwaterloo.ca computed according to scheme 2 is assigned. In other words, you must be able to pass the course based on your exam Instructors marks in order to have the lab mark count towards your final grade. Rob Gorbet DC3518 Ext. 3489 robert.gorbetuwaterloo.ca Wayne Loucks CPH1325K Ext. 4792 wayne.loucksuwaterloo.ca graded weight Carol Hulls DC2725 Ext. 5314 chullskingcong.uwaterloo.ca work scheme 1 scheme 2 Lab 1 0% 4% Teaching Assistants Lab 2 0% 4% Jeff Dungen E22365 Ext. TBA jrmdungeengmail.uwaterloo.ca Lab 3 0% 12% Bill Bishop DC2544 wdbishopece.uwaterloo.ca Midterm Exam 25% 20% Steve Marchetti srmarcheengmail.uwaterloo.ca Final Exam 75% 60% Brian Keats E21304 brian.keatsuwaterloo.ca Hai Jiang DC3562 hjiangbbcr.uwaterloo.ca ECE324/325 Course Staff I-1 Marking Scheme I-2Course Introduction Course Introduction Schedule Electronic Course Support In addition to the normal course structure (Lectures, Tutorial and Labs) Course Website: there are a number of special scheduling characteristics. • Content • Three hours of tutorial information is presented in the lecture times – Contact points during the start of the term. As a result we will have lectures during – Lecture notes the tutorial time slots for the first 2 weeks of the term. – Lab material and manual • Special tutorial Jan 9 and 10, 6:30-9:30 CPH 1346 (Each student – Lab FAQ attends 1, please sign up.) – Web pointers for both lab and lecture material • ECE 325 will have make-up lectures at 8:30 three times during the – Old exams (many with solutions) term. – Assignments Lab Signup: • Location: www.pads.uwaterloo.ca/ece324/ or • Starts Noon Friday Jan 4 www.pads.uwaterloo.ca/ece325/ or www2.pads.uwaterloo.ca/ece324/ or • URL: http://www.ece.uwaterloo.ca/signup.html www2.pads.uwaterloo.ca/ece325/ or www.ece.uwaterloo.ca/∼ece324 or • There are two lab slots to signup for this term. through the main ECE home page. The trailing / is required – Special tutorial (one of) Jan 9 or 10 (6:30-9:30 PM) for the pads addresses. ∗ individual • Protection: Access limited to uwaterloo domain or users with valid ∗ download and read lab 0 material before the tutorial. Polaris/Nexus Accounts. (Login off campus using your Nexus pass- – Regular weekly lab slot word and account). ∗ Groups of 2 (there may be room for 1 or 2 groups of one, however instructor approval is required.) Nuts and Bolts I-3 Nuts and Bolts I-4Course Introduction Course Introduction System Views Electronic Course Support (cont.) Course Newsgroup Control Computer The course newsgroup uw.ece.ece324 is to be used as a forum to discuss lab and other course related issues. This newsgroup is to be used by both Open Loop vs Closed Loop (Other courses) ECE324 and ECE 325 students. Throughout the term information about the course and the labs will be posted to the newsgroup. It is also a forum System to Control for questions (and even answers) related to many aspects of ECE 324 and (Other Courses) ECE 325. When the Temp is over 80 degrees shut the damper Paper Course Support As well as being online, course lecture notes, lab manual, and any other View A: System-Centric View handouts will be available in the DC copy centre. View B: Computer-Centric View Computer system For performing some (control) task If IN1 ox1a07 then OUT = 0x40 System to Control Nuts and Bolts I-5 Overview I-6Course Introduction Course Introduction Overview of Course Material Constraints on Performance Computer System Topics Input Processor Overview and characteristics Interface Sensors Memory Analog signals, Electrical isolation Input Signal Conditioning Shielding grounding and noise Interconnection Systems or Time synchronization External (to Processor) Input Interface Analog input, Interconnection Digital input serial and parallel Network CPU Computer Software issues (Processor plus Memory interfacing (ROM, RAM, DRAM, DMA) Memory) Bus implementations, hierarchy Output and control (see next slide) Interface Performance Analog output, Output Interface constrained by Digital output (serial and parallel) Perfomance specified external factors by computer designer Isolation, Output Signal Conditioning Noise, shielding and grounding Processor Subsystem Overview and characteristics Actuators Processor physical environment: Chassis and power Overview I-7 Overview I-8 Physical SystemCourse Introduction Course Introduction Computer Organization Memory • ECE 325 Valvano: 1.1.3, 9.3.2, 9.4 • Stores instructions or data (indistinguishable except by context of read/write). • ECE 324 ECE 222 and ECE 150 • Stored memory values are accessed using their address • Memory is connected to CPU using one (or more) buses. • ROM (Read Only Memory): usually contains the sequence of in- structions necessary to place the processor in a known start-up state. Device This may be the final state (if a monitor is used as in the lab) or this Interface ROM state may be just the starting point for a more functional operating system. Interface • RAM (Random Access Memory) used to store values and programs RAM CPU that may change. RAM • There is no distinction between ROM and RAM addresses (other than they tend to be in groups). Clock Typical (no frills) Computer Structure Background I-9 Background I-10 DeviceCourse Introduction Course Introduction Interface CPU • Interface computer to the outside world • Central Processing Unit – composed of: – Arithmetic and Logic Unit(s): to perform operations required • Converts external signals (analog or digital) to appropriate levels and by the instruction sequence timing to permit reading/writing by the processor. – Registers: Issues ∗ Data Registers: to provide internal storage for intermedi- ate results. (Also referred to as General Purpose Regis- • Signal Characteristics: ters.) – Analog (values, offset) ∗ Special Purpose Registers: · Program Counter (PC): contains the address of the – Digital (number of bits) next instruction to be read. – Noise · Instruction Register (IR): contains the current instruc- – Ground reference tion (NOT its address) · Status Register: The Program Status Register (PSW) – Current/voltage/light/magnetic contains the current status of execution (flags etc.) • Time Characteristics · Stack Pointer (SP): In CPUs that support stack-oriented operations (push, pull, jump to subroutine, return – Unidirectional/bidirectional data flow from subroutine ... ) the SP points to the top of – Source or destination responsible for control of data flow the stack. · Accumulator: A register that has restricted use within – Signalling to transfer the data some arithmetic or logic operation. – Control Unit: to read instructions from memory to provide a sequence of instructions to execute. Background I-11 Background I-12Course Introduction Course Introduction Control Signals Clock • Many operations are triggered by a control signal. • In general terms a clock provides synchronization among two or more units. • An active high control signal indicates a certain condition when it has a value of 1. • In general terms a clock may be implemented as an active edge (rising or falling) on a given signal. • An active low control signal indicates a certain condition when it has a value of 0. • In the case of a processor, such as those discussed this term, the (processor) clock signal is a source of regular, periodic rising and • A rising-edge occurs when a signal changes from a low voltage to a falling edges. higher voltage. • The processor clock can also be used as a measure of the time • A falling-edge occurs when a signal changes from a high voltage to required to execute a given instruction. a lower voltage • Changes in output signals occur in a predictable relationship with the system clock. Rising Edge Falling Edge • Input signals are sampled at a predictable time with respect to the system clock. Active High Signal RD Active Low Signal /RD Background I-13 Background I-14Course Introduction Course Introduction Systems, Actuators and Sensors Sensors and Actuators (cont.) Consider a physical system with the widest possible set of parameters. Possible Sensors Possible System Components In our case all sensors will produce an electrical signal (analog or digital). • Humans: Response times milliseconds to minutes (May be referred • Electrical:Electrical – voltmeter to as human-in-the-loop.) • Mechanical:Electrical – switches, strain gauges • Machines with moving parts: Response times milliseconds to multi- • Chemical:Electrical – pH meters ple hours • Optical:Electrical – light meter • Machines without moving parts: Response times tens of nanoseconds and up • Thermal:Electrical – temperature sensor • Chemical Reactions: Response times any • Magnetic:Electrical – speedometer Possible Actuators (Actuators in the broadest sense) Again: consider electrical inputs. • Electrical:Mechanical – motors, speakers, solenoids • Electrical:Chemical – electrodes for electroplating • Electrical:Optical – electronic displays. fibre-optic drivers • Electrical:Thermal – resistive heaters, Pelletier devices • Electrical:Magnetic – electro-magnets (or magnetic coils) Interfacing General Issues I-15 Interfacing General Issues I-16Course Introduction Course Introduction Interfacing Requirements Need for Synchronization What is to be transferred? Consider two types of transfers: • Data • Data-only transfers • Time of an event (Or a time to be associated with the event) • Transfers where the differences in time domains between source and destination matter. • Time and data associated with an event Data-only Transfers Differences between source and destination domain • Differ in view of time • Differ in physical characteristics – Differ in view of logic values – Differ in view of data meaning – Differ in view of signal ground Data – Differ in quality of signal (noise) • Differ in control – Source may provide data spontaneously – Source may provide data only when stimulated by the desti- nation System 1 System 2 An interface may need to deal with any combination of these issues. Interfacing General Issues I-17 Synchronous vs Asynchronous Systems I-18Course Introduction Course Introduction Synchronous Common View of Time Asynchronous Different Views of Time Asynchronous must share view of time to transfer data Synchronous Transfer (Common View of Time) Time Data Data System 1 System 2 System 1 System 2 Synchronous vs Asynchronous Systems I-19 Synchronous vs Asynchronous Systems I-20Embedded Systems Introduction to Embedded Systems UNIVERSITY OF WATERLOO Department of Electrical and Computer Engineering An embedded system is a special-purpose computer system designed to perform a task without the user’s knowledge of its existence. The user may provide input to the embedded system via controls and sensors but the user need not be aware of the presence of the embedded system. Section II: Some applications of embedded systems are the following: Embedded Systems • Consumer electronics – TVs, VCRs, CD players, etc. • Household appliances – washers, dryers, microwave ovens, etc. • Automotive – ABS systems, fuel injectors, transmissions, etc. • Telecommunications – handsets, cellular phones, pagers, etc. Valvano 1.1.1 January 2002 Introduction II - 1Embedded Systems Embedded Systems Embedded System Design Microprocessors vs. Microcontrollers Microprocessors: • Embedded systems come in all shapes and sizes The term, microprocessor, commonly refers to a general-purpose • Simple embedded systems are constructed out of electronics without Central Processing Unit (CPU). the need for a processor and software • Powerful, despite the name • Complex embedded systems incorporate one or more processors with • Suitable for all types of computations sophisticated control software • Require additional hardware components to support • Often, the hardware components of a complex embedded communications and storage system are designed prior to the development of any software Microcontrollers: • Hardware/software codesign is the term given to the task of The term, microcontroller, commonly refers to a Central Processing Unit simultaneously designing hardware and software components of a (CPU) that has been specialized to control the operation of a mechanical combined hardware/software system or electronic system. • Embedded system design is: • Small and cost-effective – challenging • Built-in memory – multidisciplinary – pervasive • Specialized built-in interface support for some of the following: – complex – high-speed communication – fun – parallel devices – a hard-to-acquire skill – serial devices – analog devices Introduction II - 2 Terminology II - 3Embedded Systems Embedded Systems System-On-a-Chip (SOC) Programmable Logic Device (PLD) The term, System-On-a-Chip (SOC), refers to a fully-functional The term, programmable logic device, refers to a computer chip that can computer system implemented in a single computer chip. be “rewired” to implement a custom digital circuit using primitive building blocks. Typically, a System-On-a-Chip (SOC) incorporates the following hardware components: • Several types of PLD technologies exist: – SRAM (Static Random Access Memory) • Microprocessor or a microcontroller – EEPROM (Electronically-Erasable Programmable • Communication port(s) Read-Only Memory) – Anti-fuse • Volatile storage (e.g., Random Access Memory⇒ RAM ) • Primitive building blocks include the following: • Non-volatile storage (e.g., Read-Only Memory⇒ ROM ) – Flip-flops A System-On-a-Chip (SOC) can be used to implement an embedded system – Multiplexers or a portion of an embedded system. – Lookup tables – Logic gates • Not all PLDs are created equally: – In-system programmability vs. external programming hardware – One-time programmable vs. reconfigurable Terminology II - 4 Terminology II - 5Embedded Systems System-On-a-Programmable-Chip (SOPC) UNIVERSITY OF WATERLOO Department of Electrical and Computer Engineering The term, System-On-a-Programmable-Chip (SOPC),referstoa System- On-a-Chip constructed using a high-density, reconfigurable, programmable logic device (PLD). Advantages (with respect to SOC): Section III: The Excalibur Development System • Flexible • Upgradable Disadvantages (with respect to SOC): • Potentially slower • More expensive in large quantities January 2002 Terminology II - 6The Excalibur Development System The Excalibur Development System Introduction to the Laboratory Studies Online Documentation • New laboratory studies have been created for this course • Altera provides online documentation for the Excalibur Development Board, the NIOS Processor, Quartus II and the Cygnus GnuPro – New hardware (Altera Excalibur Development Board, NIOS Toolset. Processor) – New software (Altera Quartus II, Cygnus GnuPro Toolset) • All of the documentation files are located in the following directory (for the Nexus machines in the lab): – New lab manual c:\Software\eng\ece\Altera\Excalibur\NIOS Documentation • New laboratory studies: • For your convenience, we have also placed a copy of these documen- – Lab 0: Introduction to the Excalibur Development Board tation files on the ECE 324/325 website. – Lab 1: Parallel Ports and Interrupts • Youwillneedto prioritize your reading... – Lab 2: Noise Detection and Correction – Lab 3: Analog Interfacing Introduction III - 1 Reading Materials III - 2The Excalibur Development System The Excalibur Development System Online Documentation - Suggested Reading VHDL References doc list.txt • Prior to attempting Lab 2, you will need to learn a subset of VHSIC Summary of the NIOS documentation Lab 0 Hardware Description Language (VHDL) nios getting started guide.pdf Overview of the development board and its use Lab 0 • Tutorial support will be available to assist you with learning VHDL nios tutorial.pdf Tutorial on the embedded system builder Lab 0 nios software development reference.pdf • Follow the course news group and the course web site for information Developing C software to interface with peripherals Lab 1 as Lab 2 approaches. faq sdk.txt Frequently asked questions on the software development kit Lab 1 • For additional information on VHDL, refer to the following nios pio datasheet.pdf Description of the PIO Interface Lab 1 textbooks: nios uart datasheet.pdf – VHDL, 3rd Ed. by Douglas Perry Description of the UART Interface Lab 1 nios timer datasheet.pdf – The Designer’s Guide to VHDL by Peter Ashenden Description of the Timer Interface Lab 1 faq hdk.txt – Fundamentals of Digital Logic with VHDL Design by Stephen Frequently asked questions on the hardware development kit Lab 2 Brown and Zvonko Vranesic nios spi datasheet.pdf Description of the SPI Bus Interface Lab 3 nios development board guide.pdf Detailed description of the development board Reference nios programmers reference.pdf Detailed description of the Nios processor Reference avalon.txt Detailed description of the Avalon Bus Interface Reference Reading Materials III - 3 Reading Materials III - 4The Excalibur Development System The Excalibur Development System The Excalibur Development Board Sample Excalibur Structural Layout A diagram of the Excalibur Development Board is shown below: External External RAM FLASH Nios Embedded Processor Development Board Figure 1. Nios Development Board NIOS Processor Internal ROM Avalon Interconnection Bus Interfaces (Altera or personal) CPLD and Memory on Excalibur This diagram is reprinted with permission from Altera Corporation Excalibur Development III - 5 Excalibur Development III - 6 (Internal) DevicesThe Excalibur Development System The Excalibur Development System APEX EP20K200E Programmable Logic Device APEX EP20K200E Programmable Logic Device (cont.) • Most important device on the Altera Excalibur Development Board A detailed datasheet for these devices is available on Altera’s web site at: • Provides the programmable hardware to implement the SOPC (SRAM http://www.altera.com/literature/ds/apex.pdf Based) Logic Element • May be programmed to implement a complete computer system The basic logic element in an APEX IC is shown below: • Capacity for custom hardware development • Wired to connectors so the pinouts of the device are fixed – Refer to the NIOS Development Board Guide for the pinouts – Unused pins must be configured as tri-stated inputs – Failure to set the pins appropriately can damage the APEX device Excalibur Development III - 7 Excalibur Development III - 8The Excalibur Development System The Excalibur Development System Operating Modes The NIOS Embedded Processor • Implements the Central Processing Unit (CPU) and all internal sys- tem peripherals • Two versions exist: 16-bit and 32-bit • 33 MHz clock speed (when using the Excalibur Development Board) • Hardware development tools allow you to select the following pro- cessor attributes: – Instruction width (16-bit vs. 32-bit) – Address width – Internal peripherals – External peripheral interfaces Excalibur Development III - 9 Excalibur Development III - 10

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