CMOS digital integrated circuits analysis and design notes

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CHAPTER 1 INTRODUCTION 1.1. Historical Perspective The electronics industry has achieved a phenomenal growth over the last few decades, mainly due to the rapid advances in integration technologies and large-scale systems design. The use of integrated circuits in high-performance computing, telecommunica- tions, and consumer electronics has been growing at a very fast pace. Typically, the required computational and information processing power of these applications is the driving force for the fast development of this field. Figure 1.1 gives an overview of the prominent trends in information technologies over the next decade. The current leading- edge technologies (such as low bit-rate video and cellular communications) already provide the end-users a certain amount of processing power and portability. This trend is expected to continue, with very important implications for VLSI and systems design. One of the most important characteristics of information services is their increasing need for very high processing power and bandwidth (in order to handle real-time video, for example). The other important characteristic is that the information services tend to become more personalized, which means that the information processing devices must be more intelligent and also be portable to allow more mobility. This trend towards portable, distributed system architectures is one of the main driving forces for system integration, even though it does not preclude a concurrent and equally important trend towards centralized, highly powerful information systems such as those required for network computing (NC) and video services. As more and more complex functions are required in various data processing and telecommunications devices, the need to integrate these functions in a small package is also increasing. The level of integration as measured by the number of logic gates in a2 monolithic chip has been steadily rising for almost three decades, mainly due to the rapid progress in processing technology and interconnect technology. Table 1.1 shows the evolution of logic complexity in integrated circuits over the last three decades, and marks CHAPTER 1 the milestones of each era. Here, the numbers for circuit complexity should be viewed only as representative measures to indicate the order-of-magnitude. A logic block can contain anywhere from 10 to 100 transistors, depending on the function. State-of-the-art ULSI chips, such as the DEC Alpha or the INTEL Pentium, contain 3 to 6 million transistors. Note that the term VLSI has been used continuously even for chips in the ULSI (Ultra Large Scale Integration) category, not necessarily abiding by the distinction in Table 1.1. I Video-on-demand I I Speech processing/recognition C I- Wireless/cellular data communication c I Data communication Multi-media applications I Consumer electronics I Portable computers I Mainframe co I Personal computers I I Network computers I 1970 1980 1990 2000 Figure 1.1. Prominent "driving" trends in information service technologies. ERA DATE COMPLEXITY ( of logic blocks per chip) Single transistor 1958 1 Unit logic (one gate) 1960 1 Multi-function 1962 2 - 4 Complex function 1964 5 - 20 Medium Scale Integration (MSI) 1967 20 - 200 Large Scale Integration (LSI) 1972 200 - 2,000 Very Large Scale Integration (VLSI) 1978 2,000 - 20,000 Ultra Large Scale Integration (ULSI) 1989 20,000 - ? Table 1.1. Evolution of logic complexity in integrated circuits.The monolithic integration of a large number of functions on a single chip usually 3 provides: Introduction Less area/volume and therefore, compactness Less power consumption Less testing requirements at system level Higher reliability, mainly due to improved on-chip interconnects Higher speed, due to significantly reduced interconnection length Significant cost savings Therefore, the current trend of integration will continue in the foreseeable future. Advances in device manufacturing technology allow the steady reduction of minimum feature size (such as the minimum channel length of a transistor or an interconnect width realizable on chip). Figure 1.2 shows the evolution of the minimum feature size of transistors in integrated circuits, starting from the late 1970s. In 1980, at the beginning of the VLSI era, the typical minimum feature size was 2 pm, and a feature size of 0.3 gm was expected around the year 2000. The actual development of the technology, however, has far exceeded these expectations. A minimum feature size of 0.25 gm was achieved by 1995. The first 64-Mbit DRAM and the INTEL Pentium microprocessor chip containing more than 3 million transistors were already available by 1994, pushing the envelope of integration density. The first 4-Gbit DRAM based on 0.15 gm manufacturing technology was announced by NEC in early 1997. 4.0 i .5 -D 3-0 3.0 a) E 1.5 2 1.0 0.5 0 1975 1980 1985 1990 1995 2000 Year Figure 1.2. Evolution of minimum feature size in integrated circuits over time. When comparing the integration density of integrated circuits, a clear distinction must be made between the memory chips and logic chips. Figure 1.3 shows the level of integration over time for memory and logic chips, starting in 1970. The number of transistors per chip has continued to increase at an exponential rate over the last three decades, effectively confirming Gordon Moore's prediction on the growth rate of chip4 complexity, which was made in the early 1960s (Moore's Law). It can be observed that in terms of transistor count, logic chips contain significantly fewer transistors in any given year mainly due to large consumption of chip area for complex interconnects. CHAPTER 1 Memory circuits are highly regular, and thus more cells can be integrated with much less area for interconnects. This has also been one of the main reasons why the rate of increase of chip complexity (transistor count per chip) is consistently higher for memory circuits. 100 M 10 M 0 0. 1 M CD 0 U C a) a, 100 K 0 .0 E z 10K 1 K 70 75 80 85 90 95 2000 Year Figure 1.3. Level of integration versus time for memory chips and logic chips. Digital CMOS (Complementary Metal Oxide Semiconductor) integrated circuits (ICs) have been the driving 'force behind Very Large Scale Integration (VLSI) for high- performance computing and other scientific and engineering applications. The demand for digital CMOS ICs will be continually strong due to salient features such as low power, reliable performance, circuit techniques for high speed such as using dynamic circuits, and ongoing improvements in processing technology. It is now projected that the minimum feature size in CMOS ICs can decrease to 0.1 gum within a few years. With such a technology, the level of integration in a single chip can be on the order of several hundreds of millions of transistors for logic chips or even higher in the case of memory chips, which presents an immense challenge for chip developers inprocessing, design methodology, testing, and projectmanagement. Throughi the "divide-and-conquer" approach and more advanced design automation using corm- 5 puter-aided design (CAD) tools, ultra-large-scale problems should be solvable. Bipolar and gallium arsenide (GaAs) circuits have been used for very high speed Introduction circuits, and this practice may continue. For instance, in Monolithic Microwave Inte- grated Circuits (MMICs), GaAs MESFET (MEtal Semiconductor Field Effect Transis- tor) technology has been highly successful. However, they are still not efficient for VLSI or Ultra Large Scale Integration (ULSI) due to processing difficulties and high power consumption, although for special applications their use may continue. As long as the downward scaling of CMOS technology remains strong, other technologies are likely to remain the technology of tomorrow. 1.2. Objective and Organization of the Book The objective of this book is to help readers develop in-depth analytical and design capabilities in digital CMOS circuits and chips. The development of VLSI chips requires an interdisciplinary team of architects, logic designers, circuit and layout designers, packaging engineers, test engineers, and process and device engineers. Also essential are the computer aids for design automation and optimization. It is not possible to discuss the full spectrum of development issues in any single book. Therefore, this book concentrates on digital circuits and also presents related materials in processing and device principles essential to in-depth understanding of CMOS digital circuits. Often readers can become lost in details and fail to see the global picture. For VLSI circuit design, however, it is important that the design be done in the context of global optimization with proper boundary conditions. In fact, the beauty of integrated circuits is that the final design goal is the concerted performance of all interconnected transistors, and not of individual transistors. Therefore, the interconnect issues are almost as important as the issues of individual transistors.-No matter how well an individual transistor performs, if the technology fails to have equally good interconnects, the total performance can be very poor due to large parasitic capacitances and resistances; these translate into a large delay in the interconnection lines between transistors or logic gates. This volume is intended as a comprehensive textbook for senior-level undergradu- ate students and first-year graduate students in an advanced course on digital circuit design. The material presented in this book should also be very useful to practicing VLSI design engineers. Most of the material presented has been taught over several years in undergraduate and graduate-level courses in the department of electrical and computer engineering at the University of Illinois at Urbana-Champaign. It is assumed that the readers of this book already have sufficient fundamental background on semiconductor devices, electronic circuit design and analysis, and logic theory. While the interactions among logic design, circuit design, and layout design are strongly emphasized throughout the text, the main focus is on transistor-level circuit design and analysis. This requires a fair amount of detailed current and voltage calculations, as well as a good understanding of how device characteristics affect overall circuit performances, such as propagation delay, noise margins, and power dissipation. The relational ordering and extent of the topics covered in a typical digital integrated circuits course are depicted in Fig. 1.4. First, a fundamental knowledge of basic device physics is required to understand and use various MOSFET device models in circuitwill shift from single of device fundamentals, the emphasis 6 analysis. Following a review to more complex circuits, such as inverters, and then devices to simple two-transistor the breadth of each as we move to more advanced topics, logic circuits. We will see that CHAPTER 1 may be a large number of different variations also increases significantly. In fact, subject we will circuits and systems. Consequently, considered for implementing complex system implementations and compare examples for large-scale examine representative and manufacturability. merits in terms of performance, reliability, their relative Physics Device Electronics Increasing Two-Transistor Complexity Circuits (inverters) mbinational and Sequential Logic Circuits r u ar res i. VLSI Sub-Systems Multipliers ROMs, RAMs, PLAs 1 Adders, i System-Related issues, Reliability, Manufacturability, Testability - - Breadth of Topics circuits course. of topics covered in a typical digital integrated Figure 1.4. The ordering issues. Representative inte- with a review of fabrication-related The book begins in the beginning, in techniques are summarized very briefly grated circuit fabrication the reader with the simple view of process flow and to provide order to establish a the extent of MOS device related to processing. The level and necessary terminologies circuit design and book are specifically geared toward hands-on physics covered in this are relatively simple. The hence, most of the device models used analysis applications; however, the certain limitations on the accuracy; choice of simple device models imposes and on the understanding of basic design concepts emphasis is primarily on the clear the early estimates for circuit performance during importance of generating meaningful tools in VLSI of computer-aided circuit simulation design stages. The very importantrole contains a large number of computer simulation design is also well recognized. The book SPICE (Simulation Program with Integrated examples and exercise problems based on circuit a de facto standard in transistor-level Circuit Emphasis), which has become to the platforms. An entire chapter is devoted simulation in a wide range of computing the models implemented in SPICE, including examination and comparison of MOSFET will Computer simulation is, and of various device model parameters. identification continue to be, an essential part of the design process, both for performance verification 7 and for fine-tuning of circuits. However, the emphasis on simulation must be well- balanced with the emphasis on hands-on design and analytical estimates, so that the Introduction significance of the latter is not overwhelmed by the extensive use of computer-aided techniques. The main focus of this book is on CMOS digital integrated circuits, but a significant amount of material on nMOS digital circuits is also presented. Although CMOS has become the technology of choice in many applications in recent years, the fundamental concepts of nMOS logic provide a strong basis both for the conceptual understanding and for the development of CMOS designs. Chapters 5 through 9 are devoted exclusively to the analysis and design of basic CMOS and also some nMOS digital circuits. Fig. 1.5 shows a simple "family tree" for digital integrated circuits that clarifies the classification and relations among different types of circuits. Based on the fundamental operating principles, the circuits are classified into two main categories, i.e., static circuits and dynamic circuits. The static CMOS circuits are further divided into sub-categories such as classical (fully complementary) CMOS circuits, transmission-gate logic circuits, pass- transistor logic circuits and cascade voltage switch logic (CVSL) circuits. The dynamic CMOS circuits are divided into sub-categories such as domino logic, NORA, and true single-phase clock (TSPC) circuits. Figure .5 Classification of CMOS digital circuit issues, the accurate prediction and 8 In addition to transistor-level circuit reduction of interconnect parasitics has become a very significant topic in high- integrated circuits, especially for sub-micron technologies. A large CHAPTER 1 performance digital portion of Chapter 6 is therefore devoted to interconnect effects. Semiconductor memo- ries are covered in detail in Chapter 10. Specific emphasis is given to the design and static and dynamic memory types and to comparisons of their operation of different characteristics. One chapter of the book is devoted to bipolar transistors and performance to play an important role in the high- to bipolar/BiCMOS digital circuits, which continue circuits in this book performance digital circuits arena. The inclusion of bipolar-based of BiCMOS design techniques may be puzzling to some readers, but the significance text on digital design. One chapter is entirely cannot be neglected in a comprehensive input/output (I/O) circuits and related issues, including ESD protection, dedicated to and latch-up prevention. Various VLSI design styles, level shifting, super-buffer design, design issues are discussed in large-scale design considerations, and system-level 14. Finally, two chapters on design for manufacturability and design for Chapter testability cover many of the important topics, such as yield estimation, statistical design, attention in the context of large-scale and system testability, which deserve special integrated circuit design. of this text includes an entirely new chapter, Low-Power CMOS The second edition systems and the need to limit Logic Circuits. The increasing prominence of portable in very high density ULSI chips have power consumption (and hence, heat dissipation) design in recent years. In led to rapid and very interesting developments in low-power must be combined with the most cases, the requirements of low power consumption of higher integration density and higher circuit performance. In equally demanding tasks we feel that low-power design of digital integrated circuits view of these developments, chapter. Here, various aspects of power consumption are should be treated in a separate discussed in detail and strategies are introduced to reduce the power dissipation. course The chapters are organized in order to allow several different variations of plans and self-study programs. A number of chapters can be grouped together to accommodate a specific course syllabus, and others can be skipped without a significant loss of continuity. Each chapter contains a large number of solved problems and examples, integrated into the text to enhance the understanding of the material at hand. Also, a collection of problems, some of which are geared specifically for computer-based SPICE simulation, is provided at the end of each chapter. 1.3. A Circuit Design Example To help form a global picture of the digital circuit design cycle, in this chapter we begin exercise wherein we, as circuit designers, start from a with a "once over lightly" design circuit is first translated into a logic diagram along with design specifications. The logic circuit and the initial layout is done. From the layout, all of the important CMOS parasitics are calculated by using a circuit extraction program. Once a full circuit description is obtained from the initial layout, we analyze the circuit for DC and transient performance by using the circuit-level simulation program, SPICE, and then compare the results with the given design specifications. If the initial design fails to meet any one ofthe specifications, which is the case in this exercise, we devise an improved circuit design 9 to meet the design objective. Then the improved design will be implemented into a new layout and the design-analysis cycle will be repeated until all of the design specifications Introduction are met. The simplified flow of this circuit design procedure is illustrated in Fig. 1.6. Note that the topics covered in this textbook concern primarily the two important steps enclosed in the dotted box, namely, VLSI design and design verification. System Requirements Logic diagram / description Technology Design Rules Device Models Design Rule Checking Circuit Simulation (SPICE) Fail Mask Generation Silicon Processing To: Wafer Testing Packaging Reliability Qualification Figure 1.6. The flow of circuit design procedures.1 Example 1.1; CHAPTER 0.8-,um, we will design a one-bit binary full-adder circuit using In the following example, The design specifications are twin-well CMOS technology. and carryout signals 1.2 ns (worst case) Propagation delay times of sum times of sum and carry-out signals 1.2 ns (worst case) Transition delay 2 Circuit area 1500 ,m power dissipation ( VDD = 5 V andfmax = 20 MHz) 1 mW Dynamic description of the binary adder circuit. We start our design by considering the Boolean variables (addend bits), and let C represent the Let A and B represent the two input two-output combinational circuit carry-in bit. The binary full adder is a three-input, which satisfies the truth table below. A B C sum_ out carry_ out 0 0 0 00 1 1 0 0 0 1 0 0 1 0 - sum-out 1 0 11 0 Full Adder 1 0 1 0 0 - carry-out 1 0 1 C - 1 0 0 1 1 1 0 1 11 1 two combinational The sumout and carry-out signals can be found as the following Boolean functions of the three input variables, A, B and C. sumout =AEBEC =ABC+ABC+ABC+ACB carry out = AB + AC + BC instead of A gate-level realization of these two functions is shown in Fig. 1.7. Note that two functions independently, we use the carry-out signal to generate the sum realizing the can also be expressed as output, since the output sumout =ABC+(A+B+C)carryoutThis implementation will ultimately reduce the circuit complexity and, hence, save chip 11 area. Also, we identify two separate sub-networks consisting of several gates (high- lighted with dashed boxes) which will be utilized for the transistor-level realization of the Introduction full-adder circuit. A B C A B C sum Figure 1.7. Gate-level schematic of the one-bit full-adder circuit. For translating the gate-level design into a transistor-level circuit description, we note that both the sum..out and the carryout functions are represented by nested AND- OR-NOR structures in Fig. 1.7. Each such combined structure (complex logic gate) can be realized in CMOS as follows: the AND terms are implemented by series-connected nMOS transistors, and the OR terms are implemented by parallel-connected nMOS transistors. The input variables are applied to the gates of the nMOS (and the complemen- tary pMOS) transistors. Thus, the nMOS net may consist of nested series-parallel ,connections of nMOS transistors between the output node and the ground. Once the nMOS part of a complex CMOS logic gate is realized, the corresponding pMOS net, which is connected between the output node and the power supply, is obtained as the dual network of the nMOS net. The resulting transistor-level design of the CMOS full-adder circuit is shown in Fig. 1.8. Note that the circuit contains a total of 14 nMOS and 14 pMOS transistors, together with the two CMOS inverters which are used to generate the outputs. In this specific example, it can also be shown that the dual (pMOS) network is actually equivalent to the nMOS network for both the sum_out and the carry-out functions, which leads to a fully symmetric circuit topology. The alternate circuit diagram obtained by applying this principle of symmetry in shown in Fig. 1.9. Note that the Boolean functions realized by the circuits shown in Fig. 1.8 and Fig. 1.9 are identical; yet the symmetric circuit topology shown in Fig. 1.9 significantly simplifies the layout. These issues will be discussed in detail in Chapter 7.12 Initially, we will design all nMOS and pMOS transistors with a (WIL) ratio of (2 allowed in this particular technology. um/IO;8 tm), which is the minimum transistor size obviously not an optimum solution, may be This initial sizing of transistors, which is CHAPTER 1 on the performance characteristics of the adder circuit. Choos- changed later depending in the initial design stage usually provides a simple, first- ing minimum-size transistors in developing a cut verification of the circuit functionality and helps the designer simple initial layout. V-n sum Figure 1.8. Transistor-level schematic of the one-bit full-adder circuit. VDD Figure 1.9. Alternate transistor-level schematic of the one-bit full-adder circuit (note that the and pMOS networks are completely symmetric). nMOS Next, the initial layout of the full-adder circuit is generated. Here we use a regular, 13 gate-matrix layout style in order to simplify the overall geometry and the signal routing. The initial layout using minimum-size transistors is shown in Fig. 1.10. Note that in this Introduction initial adder cell layout, all nMOS and pMOS transistors are placed in two parallel rows, between the horizontal power supply and the ground lines (metal). All polysilicon lines are laid out vertically. The area between the n-type and p-type diffusion regions is used for running local metal interconnections (routing). Also note that the diffusion regions of neighboring transistors have been merged as much as possible, in order to save chip area. The regular gate-matrix layout style used in this example also has the inherent advantage of being easily adaptable to computer-aided design (CAD). The silicon area occupied by 2 this full-adder layout is (21 gtm x 54 gtm) = 1134 ,um . A B C I I Ale-. rD -I-Ae - - -u4- u - - - DD .. .... .... .... .. ..... .... ... .. .. .. ..... i ..... ...... ...... i.-'', gg .................................. -................. _g0, o .... .... ............... ....... ... EHEC _: 1 .' ' 1 l l::::: ........................ ,,i , IEI I'm - i iII ND iN ' : US U CO SUM Figure 1.10. Initial layout of the full-adder circuit using minimum-size transistors. The designer must confirm, using an automatic design rule checker (DRC) tool, that none of the physical layout design rules are violated in this adder layout. This is usually done concurrently during the graphical entry of the layout. The next step is to extract the parasitic capacitances and resistances from the initial layout, and then to use a detailed circuit simulation tool (e.g. SPICE) to estimate the dynamic performance of the adder circuit. Thus, we are now in the design verification stage of the design-flow diagram shown in Fig. 1.6. The parasitic extraction tool reads in the physical layout file, analyzes the various mask layers to identify transistors, interconnects and contacts, calculates the parasitic capacitances and the parasitic resistances of these structures, and finally prepares a SPICE input file that accurately describes the circuit (see Chapter 4). The extracted circuit file is now simulated using SPICE in order to determine its dynamic performance. The three input waveforms (A, B and C) are chosen so that all of the eight possible input combinations are applied consecutively to the full-adder circuit. Assuming that the outputs of this adder circuit may drive a similar circuit, both output nodes are loaded with capacitors which represent the typical input capacitance of a full adder. Figure 1.11 shows the simulated input and output waveforms. Unfortunately, thedoes not meet all of the design specifications. The simulation results show that the circuit signals are found to violate the propagation delay times of the sum_out and carry-out are not capable of properly driving timing constraints, since the minimum-size transistors CHAPTER 1 the capacitive output loads. Minimum Size Full Adder, Extracted 0 d10 . . .' Ccory IN 4.0 2.0 0.0 . . . . . . .. . 10 I- . . . . . . . . . 2 I0 1 . . . .. . . . 0 x10 2.0 E0 .: Carry OUT o. 5.0 2.0 . . . . . . . . . . . . I . . . . . . . . . . . . . . . I . .1 I -S . 0ยข .: SUM 5 \ 9 5 t - \ 1. 0.0 40_...-t 1.11. Simulated input and output waveforms of the full-adder circuit. Figure In particular, the worst-case delay is found to be about 2.0 ns, whereas the timing requirements dictate a maximum delay of 1.2 ns. Figure 1.12 shows the signal propaga- tion delay of both inputs in detail during one of the worst-case input transitions. Design modifications will be necessary to correct this problem. Thus, we go back to the layout design stage. One approach to increase switching speed, and thus, to reduce delay times, would be the to increase the (WIL) ratios of all transistors in the circuit. However, increasing transistor (WIL) ratios also increases the gate, source, and drain areas and, consequently, increases the parasitic capacitances loading the logic gates. Hence, the resizing oftransistors is strictly an iterative process which involves several cycles of consecutive executivee 15 layout modification, circuit extraction, and simulation. Since the carry_out signal I is is used used to generate the sum output, reducing the delay in the carry_out stage should generally dly take take Introduction auhigherdedority. a higher prio Also, one should be careful to consider all possible input tra isitions: Optimiing Optimizing ti te propagation delay for one particular input transition only may resuina alt in an unintended ices fpoaain eay uigohrtastos F iger 1.12. 18 19 20 21 22 23 24 255 Time nsl Figure 1.12. Simulated output waveforms of the full adder circuit with minimum transistor -ansistor dimensions, dimensions, sl showing the signal propagation delay during one of the worst-case transitions. ons. While While w, we resize the nMOS and pMOS transistors in the full-adder circuit to meet rieetthe the timing timing requir requirements, we can also reorganize the whole layout in order to achieve  a a more more compact compact placement, plac to increase silicon area utilization, and to reduce the interconnection section parasitics within Vparasitics wii the cell. The resulting cell layout is shown in Fig. 1.12. The new -W full- full- 2 adder adder layout occupies layout an area of (43 Atm x 90 gm) = 1290 ,um , which is about 14% b larger larger than than the the initiz initial layout (despite rather aggressive resizing of the transistor dimensions) )ns) but but 2 still below the pre-set still below th upper limit of 1500 ,um . For For the the optimized full-adder circuit, we find that all propagation and transition on (rise (rise and and fall) fall) dela delay times are now within the specified limits, i.e., less than 1.2 ns. Figure ire 1 1.14 14 shows shows the the signal si propagation delay of both inputs during the same worst-case e input input transition transition depicted de in Fig. 1.11. Note that the propagation delay is about 1.0 0 ns, ns a a reduction reduction of of.50%. The dynamic power dissipation of this circuit is estimated to be be 460 460 AW. lW. Thus, Thus, the th circuit now satisfies the design specifications given in the beginning. ning.16 A B C CHAPTER 1 01...lDFF; I NWFLL _ POLY = MET-1 E MET 2 MU Figure 1.13. Modified layout of the full-adder circuit, with optimized transistor dimensions. Worst Case Delay, otimized Size Transistors, EXTRACTED INPUT .. . CARRY I . SUM 5 4 3 '0 A i -_____-L ___-__ .1 ______ - _ 2.5 -H 2 ..... . ....... .. ..... .. .. .... .. .. .. . .. ..... ... . 1 .. ...... .... .. .. ............ .... ... .. ....... .. ....... 0 q n 1 n q .'1 1 ''I .1.'7.....A.. 1 8 19 20 2 1 2 2 23 2 Z4 25b Time ns the full-adder circuit with optimized transistor Figure 1.14. Simulated output waveforms of dimensions, showing the signal propagation delay during the same worst-case transition.The full-adder circuit designed in this example can now be used as the basic building 17 block of an 8-bit binary adder, which accepts two 8-bit binary numbers as input and produces the binary sum at the output. The simplest such adder can be constructed by a Introduction cascade-connection of eight full adders, where each adder stage performs a two-bit addition, produces the corresponding sum bit, and passes the carry output on to the next stage. Hence, this cascade-connected adder configuration is called the carry ripple adder (Fig. 1. 15). The overall speed of the carry ripple adder is obviously limited by the delay of the carry bits rippling through the carry chain; therefore, a fast carryout response becomes essential for the overall performance of the adder chain. S 7 .. . C, AO Bo A B A B A B 1 1 2 2 7 7 Figure 1.15. Block diagram of a carry ripple adder chain consisting of full adders. Figure 1.16 shows the mask layout of a 4-bit-section of the carry ripple adder circuit which is designed by simply cascading full-adder cells to form a regular array. Note that the input signals Ai and Bi are applied to a row of pins along the lower boundary of the array, while the output signals Si (sum bits) are made available along the upper boundary of the array. This arrangement of the input and output pins simplifies signal routing by placing the input bus below, and the output bus above the adder array. Also note that no Si S S3 S0 9 MN 4 MD '0 D0 1 Da M0 2 2 3 3 Figure 1.16. Mask layout of the 8-bit carry ripple adder array.18 additional routing is necessary for the carry signal, since the carry-in and carryout pin locations of consecutive full-adder cells are aligned against each other. Such structures are routinely used in circuits where a large number of arithmetic operations are required, CHAPTER 1 such as arithmetic-logic units (ALUs) and digital signal processing (DSP) circuits. The overall performance of the multi-bit adder can be further increased by various measures, and some of these issues will be discussed in later chapters. The simulated input and output waveforms of the 8-bit binary adder circuit are shown in Fig. 1.17 for a series of sample input vectors. It can be seen that the sum bit of the last adder stage is typically generated last, and the overall delay can be as much as 7 ns. 8 Sit Fl1 Add., A (Bbit) 00 e14 I9 8 (Bbtt) 00 64 IX9 12 X2 C."r IN, SUM(LS) SUM(1) SUM(2) SUM(4) SUM(5) SUM(6) SUM(7) SUM(MS _ 7.0 a: SUM(7) SN f Lot Adder Stoge 70 SUM(M50) Corey OUT of Lost Adder Stage I_01 710 Add., SUM(WB) Stage cwy of Last l0 Ie .-. .- I Figure 1.17. Simulated input and output waveforms of the 8-bit carry ripple adder circuit, showing a maximum signal propagation delay of about 7 ns.This example has shown us that the design of CMOS digital integrated circuits 19 involves a wide range of issues, from Boolean logic to gate-level design, to transistor- level design, to physical layout design, and to parasitics extraction followed by detailed Introduction circuit simulation for design tuning and performance verification. In essence, the final output of integrated circuit design is the mask data from which the actual circuit is fabricated. Thus, it is important to design the layout and, hence, the mask set such that the fabricated integrated circuits meet test specifications with a high yield. To achieve such a goal, designers perform extensive simulations using computer models extracted from the layout data and iterate the design until simulated results meet the specifications with sufficient margins. In the following chapters, we will discuss the fabrication of MOS transistors using a set of masks, layout design rules, and electrical 'properties of MOS transistors and their computer models, before discussing the most basic CMOS inverter circuit.

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