Lecture notes on CMOS VLSI design

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Chapter 1 Introduction to CMOS Design This chapter provides a brief introduction to the CMOS (complementary metal oxide semiconductor) integrated circuit (IC) design process (the design of "chips"). CMOS is used in most very large scale integrated (VLSI) or ultra-large scale integrated (ULSI) circuit chips. The term "VLSI" is generally associated with chips containing thousands or millions of metal oxide semiconductor field effect transistors (MOSFETs). The term "ULSI" is generally associated with chips containing billions, or more, MOSFETs. We'll avoid the use of these descriptive terms in this book and focus simply on "digital and analog CMOS circuit design." We'll also introduce circuit simulation using SPICE (simulation program with integrated circuit emphasis). The introduction will be used to review basic circuit analysis and to provide a quick reference for SPICE syntax. 1.1 The CMOS IC Design Process The CMOS circuit design process consists of defining circuit inputs and outputs, hand calculations, circuit simulations, circuit layout, simulations including parasitics, reevaluation of circuit inputs and outputs, fabrication, and testing. A flowchart of this process is shown in Fig. 1.1. The circuit specifications are rarely set in concrete; that is, they can change as the project matures. This can be the result of trade-offs made between cost and performance, changes in the marketability of the chip, or simply changes in the customer's needs. In almost all cases, major changes after the chip has gone into production are not possible. This text concentrates on custom IC design. Other (noncustom) methods of designing chips, including field-programmable-gate-arrays (FPGAs) and standard cell libraries, are used when low volume and quick design turnaround are important. Most chips that are mass produced, including microprocessors and memory, are examples of chips that are custom designed. The task of laying out the IC is often given to a layout designer. However, it is extremely important that the engineer can lay out a chip (and can provide direction to the layout designer on how to layout a chip) and understand the parasitics involved in the 2 CMOS Circuit Design, Layout, and Simulation layout. Parasitics are the stray capacitances, inductances, pn junctions, and bipolar transistors, with the associated problems (breakdown, stored charge, latch-up, etc.). A fundamental understanding of these problems is important in precision/high-speed design. Define circuit inputs and outputs (Circuit specifications) Hand calculations and schematics Circuit simulations Layout Re-simulate with parasitics No Prototype fabrication Test and evaluate No, fab problemD i c uit5 0' sPec Problem oe s th e c r meet specs? Yes Production Figure 1.1 Flowchart for the CMOS IC design process. Chapter 1 Introduction to CMOS Design 3 1.1.1 Fabrication CMOS integrated circuits are fabricated on thin circular slices of silicon called wafers. Each wafer contains several (perhaps hundreds or even thousands) of individual chips or "die" (Fig. 1.2). For production purposes, each die on a wafer is usually identical, as seen in the photograph in Fig. 1.2. Added to the wafer are test structures and process monitor plugs (sections of the wafer used to monitor process parameters). The most common wafer size (diameter) in production at the time of this writing is 300 mm (12 inch). A die fabricated with other dice on the silicon wafer D Top (layout) view 1 ' Side (cross-section) view Wafer diameter is typically 100 to 300 mm. Figure 1.2 CMOS integrated circuits are fabricated on and in a silicon wafer. Shown are 150, 200, and 300 mm diameter wafers. Notice the reflection of ceiling tiles in the 300 mm wafer. The ICs we design and lay out using a layout program can be fabricated through MOSIS (http://mosis.com) on what is called a multiproject wafer; that is, a wafer that is comprised of chip designs of varying sizes from different sources (educational, private, government, etc.). MOSIS combines multiple chips on a wafer to split the fab cost among several designs to keep the cost low. MOSIS subcontracts the fabrication of the chip designs (multiproject wafer) out to one of many commercial manufacturers (vendors). MOSIS takes the wafers it receives from the vendors, after fabrication, and cuts them up to isolate the individual chip designs. The chips are then packaged and sent to the originator. A sample package (40-pin ceramic) from a MOSIS-submitted student design is seen in Fig. 1.3. Normally a cover (not shown) keeps the chip from being exposed to light or accidental damage. 4 CMOS Circuit Design, Layout, and Simulation Figure 1.3 How a chip is packaged (a) and (b) a closer view. Note, in Fig. 1.3, that the chip's electrical signals are transmitted to the pins of the package through wires. These wires (called "bond wires") electrically bond the chip to the package so that a pin of the chip is electrically connected (shorted) to a piece of metal on the chip (called a bonding pad). The chip is held in the cavity of the package with an epoxy resin ("glue") as seen in Fig. 1.3b. The ceramic package used in Fig. 1.3 isn't used for most mass-produced chips. Most chips that are mass produced use plastic packages. Exceptions to this statement are chips that dissipate a lot of heat or chips that are placed directly on a printed circuit board (where they are simply "packaged" using a glob of resin). Plastic packaged (encapsulated) chips place the die on a lead frame (Fig. 1.4) and then encapsulate the die and lead frame in plastic. The plastic is melted around the chip. After the chip is encapsulated, its leads are bent to the correct position. This is followed by printing information on the chip (the manufacturer, the chip type, and the lot number) and finally placing the chip in a tube or reel for shipping to a company that makes products that use the chips. Example products might include chips that are used in cell phones, computers, microwave ovens, printers. Layout and Cross Sectional Views The view that we see when laying out a chip is the top, or layout, view of the die. However, to understand the parasitics and how the circuits are connected together, it's important to understand the chip's cross-sectional view. Since we will often show a layout view followed by a cross-sectional view, let's make sure we understand the difference and how to draw a cross-section from a layout. Figure 1.5a shows the layout (top) view of a pie. In (b) we show the cross-section of the pie (without the pie tin) at the line indicated in (a). To "lay-out" a pie we might have layers called: crust, filling, caramel, whipped-cream, nuts, etc. We draw these layers to indicate how to assemble the pie (e.g., where to place nuts on the top). Note that the order we draw the layers doesn't matter. We could draw the nuts (on the top of the pie) first and then the crust. When we fabricate the pie, the order does matter (the crust is baked before the nuts are added). Chapter 1 Introduction to CMOS Design 5 Figure 1.4 Plastic packages are used (generally) when the chip is mass produced. (b) Cross-sectional view Figure 1.5 Layout and cross sectional view of a pie (minus pie tin). CMOS Circuit Design, Layout, and Simulation 6 1.2 CMOS Background CMOS circuit design (the idea and basic concepts) was invented in 1963 by Frank Wanlass while at Fairchild Semiconductor, see US Patent 3,356,858, 5. The idea that a circuit could be made with discrete complementary MOS devices, an NMOS (n-channel MOSFET) transistor (Fig. 1.6) and a PMOS (p-channel) transistor (Fig. 1.7) was quite novel at the time given the immaturity of MOS technology and the rising popularity of the bipolar junction transistor (BJT) as a replacement for the vacuum tube. Figure 1.6 Discrete NMOS device from US Patent 3,356,858 5. Note the metal gate and the connection to the MOSFET's body on the bottom of the device. Also note that the source and body are tied together. The CMOS Acronym Note in Figs. 1.6 and 1.7 the use of a metal gate and the connection to the MOSFET's body on the bottom of the transistor (these are discrete devices). As we'll see later in the book (e.g., Fig. 4.3) the gate material used in a modem MOSFET is no longer metal but rather polysilicon. Strictly speaking, modem technology is not CMOS then but rather CPOS (complementary-polysilicon-oxide-semiconductor). US Patent 3,356,858 refers to the use of insulated field effect transistors (IFETs). The acronym IFET is perhaps, even today, a more appropriate descriptive term than MOSFET. Others (see the footnote on page 154) have used the term IGFET (insulated-gate-field-effect-transistor) to describe the devices. We'll stick to the ubiquitous terms MOSFET and CMOS since they are standard terms that indicate devices, design, or technology using complementary field effect devices. Figure 1.7 Discrete PMOS device from US Patent 3,356,858 5. Chapter 1 Introduction to CMOS Design 7 CMOS Inverter Figure 1.8 shows the schematic of a CMOS inverter. Note the use of a modified bipolar symbol for the MOSFET (see Fig. 4.14 and the associated discussion). Also note that the connections of the sources (the terminals with arrows) and drains are backwards from most circuit design and schematic drawing practices. Current flows from the top of the schematic to the bottom, and the arrow indicates the direction of current flow. 1 v SO 37, 3 0 y 54- / 3& 56 jL Vi s H52 53H 1 Z5 zr Figure 1.8 Inverter schematic from US Patent 3,356,858 5. When the input voltage, V, is -K(the negative supply rail), the output, V , goes to t a +V (the positive supply voltage). The NMOS device (bottom) shuts off and the PMOS device (top) turns on. When the input goes to +P, the output goes to —V turning on the NMOS and turning off the PMOS. So if a logic 0 corresponds to -Fand a logic 1 to +V, the circuit performs the logical inversion operation. This topology has several advantages over digital circuits implemented using BJTs including an output swing that goes to the power supply rails, very low static power dissipation, and no storage time delays (see Sec. 2.4.3). The First CMOS Circuits In 1968 a group led by Albert Medwin at RCA made the first commercial CMOS integrated circuits (the 4000 series of CMOS logic gates). At first CMOS circuits were a low-power, but slower, alternative to BJT logic circuits using TTL (transistor-transistor logic) digital logic. During the 1970s, the makers of watches used CMOS technology because of the importance of long battery life. Also during this period, MOS technology was used for computing processor development, which ultimately led to the creation of the personal computer market in the 1980s and the use of internet, or web, technology in the 1990s. It's likely that the MOS transistor is the most manufactured device in the history of mankind. Currently more than 95% of integrated circuits are fabricated in CMOS. For the present, and foreseeable future, CMOS will remain the dominant technology used to fabricate integrated circuits. There are several reasons for this dominance. CMOS ICs can be laid out in a small area. They can handle very high operating speeds while dissipating relatively low power. Perhaps the most important aspect of CMOS's dominance is its manufacturability. CMOS circuits can be fabricated with few defects. Equally important, the cost to fabricate in CMOS has been kept low by shrinking devices (scaling) with each new generation of technology. This also, for digital circuits, is significant because in many cases the same layout can be used from one fabrication size (process technology node) to the next via simple scaling. 8 CMOS Circuit Design, Layout, and Simulation Analog Design in CMOS While initially CMOS was used exclusively for digital design, the constant push to lower costs and increase the functionality of ICs has resulted in it being used for analog-only, analog/digital, and mixed-signal (chips that combine analog circuits with digital signal processing) designs. The main concern when using CMOS for an analog design is matching. Matching is a term used to describe how well two identical transistors' characteristics match electrically. How well circuits "match" is often the limitation in the quality of a design (e.g., the clarity of a monitor, the accuracy of a measurement, etc.). 1.3 An Introduction to SPICE The simulation program with an integrated circuit emphasis (SPICE) is a ubiquitous software tool for the simulation of circuits. In this section we'll provide an overview of SPICE. In addition, we'll provide some basic circuit analysis examples for quick reference or as a review. Note that the reader should review the links at CMOSedu.com for SPICE download and installation information. In addition, the examples from the book are available at this website. Note that all SPICE engines use a text file (a netlist) for simulation input. Generating a Netlist File We can use, among others, the Window's notepad or wordpad programs to create a SPICE netlist. SPICE likes to see files with ".cir, .sp, or .spi" (among others) extensions. To save a file with these extensions, place the file name and extension in quotes, as seen in Fig. 1.9. If quotes are not used, then Windows may tack on ".txt" to the filename. This can make finding the file difficult when opening the netlist in SPICE. Figure 1.9 Saving a text file with a ".cir" extension. Chapter 1 Introduction to CMOS Design 9 Operating Point The first SPICE simulation analysis we'll look at is the .op or operating point analysis. An operating point simulation's output data is not graphical but rather simply a list of node voltages, loop currents, and, when active elements are used, small-signal AC parameters. Consider the schematic seen in Fig. 1.10. The SPICE netlist used to simulate this circuit may look like the following (again, remember, that all of these simulation examples are available for download at CMOSedu.com): Figure 1.10 CMOS: Circuit Design, Layout, and Simulation " destroy all run print all •op Vin 1 0 DC 1 R1 1 2 1k R2 2 0 2k .end node 1 Rl -Jk node 2 -NAA f Vin, 1 V (V\ S R2, 2k X7 Figure 1.10 Operation point simulation for a resistive divider. The first line in a netlist is a title line. SPICE ignores the first line (important to avoid frustration). A comment line starts with an asterisk. SPICE ignores lines that start with a (in most cases). In the netlist above, however, the lines that start with are command lines. These command lines are used for control in some SPICE simulation programs. In other SPICE programs, these lines are simply ignored. The commands in this netlist destroy previous simulation data (so we don't view the old data), run the simulation, and then print the simulation output data. SPICE analysis commands start with a period. Here we are performing an operating point analysis. Following the .op, we've specified an input voltage source called Vin (voltage source names must start with a V, resistor names must start with an R, etc.). connected from node 1 to ground (ground always has a node name of 0 zero). We then have a Ik resistor from node 1 to node 2 and a 2k resistor from node 2 to ground. Running the simulation gives the following output: v(1) = 1.000000e+00 v(2) = 6.666667e-01 vinbranch = -3.33333e-04 The node voltages, as we would expect, are 1 V and 667 mV, respectively. The current flowing through Vin is 333 uA. Note that SPICE defines positive current flow as from the + terminal of the voltage source to the - terminal (hence, the current above is negative). CMOS Circuit Design, Layout, and Simulation 10 It's often useful to use names for nodes that have meaning. In Fig. 1.11, we replaced the names node 1 and 2 with Vin and Vout. Vin corresponds to the input voltage source's name. This is useful when looking at a large amount of data. Also seen in Fig. 1.11 is the modified netlist. "•Figure 1.11 CMOS destroy all Rl, Ik run Vin Vout -VW- print all •op Vin, 1 V ( + R2,2k Vin Vin 0 DC 1 R1 Vin Vout 1k R2 Vout 0 2k S7 .end Figure 1.11 Operation point simulation for a resistive divider. Transfer Function Analysis The transfer function analysis can be used to find the DC input and output resistances of a circuit as well as the DC transfer characteristics. To give an example, let's replace, in the netlist seen above, .op with TF V(Vout,0) Vin The output is defined as the voltage between nodes Vout and 0 (ground). The input is a source (here a voltage source). When we run the simulation with this command line, we get an output of transferjunction = 6.666667e-01 output_impedance_at_v(vout,0) = 6.666667e+02 vininput_impedance = 3.000000e+03 As expected, the "gain" of this voltage divider is 2/3, the input resistance is 3k (Ik + 2k), and the output resistance is 667 Q (lk2k). As another example of the use of the .tf command consider adding the 0 V voltage source to Fig. 1.11, as seen in Fig. 1.12. Adding a 0 V source to a circuit is a common method to measure the current in an element (we plot or print I(Vmeas) for example). Figure 1.12 CMOS Vin Rl» k Vout destroy all -W\A run I(Vmeas) Vin, 1 V( + print all TF l(Vmeas) Vin Vin Vin 0 DC 1 R1 Vin Vout 1k R2 Vout Vmeas 2k Vmeas Vmeas 0 DC 0 .end Figure 1.12 Measuring the transfer function in a resistive divider when the output variable is the current through R2 and the input is Vin. Chapter 1 Introduction to CMOS Design 11 Here, in the .tf analysis, we have defined the output variable as a current, I(Vmeas) and the input as the voltage, Vin. Running the simulation, we get an output of transferjunction = 3.333333e-04 vininput_impedance = 3.000000e+03 vmeasoutput_impedance = 1.000000e+20 The gain is I(Vmeas)/Vin or l/3k (= 333 umhos), the input resistance is still 3k, and the output resistance is now an open (Vmeas is removed from the circuit). The Voltage-Controlled Voltage Source SPICE can be used to model voltage-controlled voltage sources (VCVS). Consider the circuit seen in Fig. 1.13. The specification for a VCVS starts with an E in SPICE. The netlist for this circuit is Figure 1.13 CMOS: Circuit Design, Layout, and Simulation destroy all run print all TF V(Vout,0) Vin Vin Vin 0 DC R1 Vb 0 3k R2 Vt Vout 1k R3 Vout 0 2k E1 Vt Vb Vin 23 .end The first two nodes (Vt and Vb), following the VCVS name El, are the VCVS outputs (the first node is the + output). The second two nodes (Vin and ground) are the controlling nodes. The gain of the VCVS is, in this example, 23. The voltage between Vt and Vb is 23-Vin. Running this simulation gives an output of transferjunction = 7.666667e+00 output_impedance_at_v(vout,0) = 1.333333e+03 vininput_impedance = 1.000000e+20 Notice that the input resistance is infinite. Figure 1.13 Example using a voltage-controlled voltage source. CMOS Circuit Design, Layout, and Simulation 12 An Ideal Op-Amp We can implement a (near) ideal op-amp in SPICE with a VCVS or with a voltage- controlled current source (VCCS), Fig. 1.14. It turns out that using a VCCS to implement an op-amp in SPICE results, in general, in better simulation convergence. The input voltage, the difference between nodes nl and n2 in Fig. 1.14, is multiplied by the transconductance G (units of amps/volts or mhos) to cause a current to flow between n3 and n4. Note that the input resistance of the VCCS, the resistance seen at nl and n2, is infinite. G, gain Voltage-Controlled Current Source (VCCS) Gl n3 n4 nl n2 G Figure 1.14 Voltage-controlled current source in SPICE. Figure 1.15 shows the implementation of an ideal op-amp in SPICE along with an example circuit. The open-loop gain of the op-amp is a million (the product of the VCCS's transconductance with the 1-ohm resistor). Note how we've flipped the polarity of the (SPICE model of the) op-amp's input to ensure a rising voltage on the noninverting input (+ input) causes Vout to increase. The closed-loop gain is -3 (if this isn't obvious then the reader should revisit sophomore circuits before going too much further in the book). Vout Rin, Ik V\A/— Vin, IV ( I Rf,3k Rin, Ik Vout Vin, IV ( I Figure 1.15 An op-amp simulation example. Chapter 1 Introduction to CMOS Design 13 The Subcircuit In a simulation we may want to use a circuit, like an op-amp, more than once. In these situations we can generate a subcircuit and then, in the main part of the netlist, call the circuit as needed. Below is the netlist for simulating, using a transfer function analysis, the circuit in Fig. 1.15 where the op-amp is specified using a subcircuit call. Figure 1.15 CMOS: Circuit Design, Layout, and Simulation destroy all run print all .TF V(Vout,0) Vin Vin Vin 0 DC 1 Rin Vin Vm 1k Rf Vout Vm 3k X1 Vout 0 vm ldeal_op_amp .subckt ldeal_op_amp Vout Vp Vm G1 Vout 0 Vm Vp 1MEG RL Vout 0 1 .ends .end Notice that a subcircuit call begins with the letter X. Note also how we've called the noninverting input (the + input) Vp and not V+ or +. Some SPICE simulators don't like + or - symbols used in a node's name. Further note that a subcircuit ends with .ends (end subckt). Care must be exercised with using either .end or .ends. If, for example, a .end is placed in the middle of the netlist all of the SPICE netlist information following this .end is ignored. The output results for this simulation are seen below. Note how the ideal gain is -3 where the simulated gain is -2.99999. Our near-ideal op-amp has an open-loop gain of one million and thus the reason for the slight discrepancy between the simulated and calculated gains. Also note how the input resistance is Ik, and the output resistance, because of the feedback, is essentially zero. transferjunction = -2.99999e+00 output_impedance_at_v(vout,0) = 3.999984e-06 vininput_impedance = 1.000003e+03 DC Analysis In both the operating point and transfer function analyses, the input to the circuit was constant. In a DC analysis, the input is varied and the circuit's node voltages and currents (through voltage sources) are simulated. A simple example is seen in Fig. 1.16. Note how we are now plotting, instead of printing, the node voltages. We could also plot the current through Vin (plot Vinbranch). The .dc command specifies that the input source, Vin, should be varied from 0 to 1 V in 1 mV steps. The x-axis of the simulation results seen in the figure is the variable we are sweeping, here Vin. Note that, as expected, the slope of the Vin curve is one (of course) and the slope of Vout is 2/3 (= Vout/Vin). CMOS Circuit Design, Layout, and Simulation 14 "»Figure 1.16 CMOS' destroy all R1 l k Vin run Vout plot Vin Vout .dcVinO 1 1m R2,2k Vin, 1 V ( + Vin Vin 0 DC 1 R1 Vin Vout 1k R2 Vout 0 2k X 7 .end Figure 1.16 DC analysis simulation for a resistive divider. Plotting IV Curves One of the simulations that is commonly performed using a DC analysis is plotting the current-voltage (IV) curves for an active device (e.g., diode or transistor). Examine the simulation seen in Fig. 1.17. The diode is named Dl. (Diodes must have names that start with a D.) The diode's anode is connected to node Vd, while its cathode is connected to '"Figure 1.17 CMOS" destroy all run let ID=-Vinbranch plot ID Vin .dcVinO 1 1m Vin Vin 0 DC 1 R1 VinVdlk D1 Vd 0 mydiode .model mydiode D .end Figure 1.17 Plotting the current-voltage curve for a diode. Chapter 1 Introduction to CMOS Design 15 ground. This is our first introduction to the .model specification. Here our diode's model name is mydiode. The .model parameter D seen in the netlist simply indicates a diode model. We don't have any parameters after the D in this simulation, so SPICE uses default parameters. The interested reader is referred to Table 2.1 on page 47 for additional information concerning modeling diodes in SPICE. Note, again, that SPICE defines positive current through a voltage source as flowing from the + terminal to the - terminal (hence why we defined the diode current the way we did in the netlist). Dual Loop DC Analysis An outer loop can be added to a DC analysis, Fig. 1.18. In this simulation we start out by setting the base current to 5 \xA and sweeping the collector-emitter voltage from 0 to 5 V in 1 mV steps. The output data for this particular simulation is the trace, seen in Fig. 1.18, with a label of "Ib=5u." The base current is then increased by 5 uA to 10 A, and the collector-emitter voltage is stepped again (resulting in the trace labeled "Ib=10u". This continues until the final iteration when lb is 25 uA. Other examples of using a dual-loop DC analysis for MOSFETIV curves are found in Figs. 6.11, 6.12, and 6.13. Figure 1.18 Plotting the current-voltage curves for an NPN BJT. Transient Analysis The form of the transient analysis statement is .tran tstep tstop tstart tmax uic where the terms in are optional. The tstep term indicates the (suggested) time step to be used in the simulation. The parameter tstop indicates the simulation's stop time. The starting time of a simulation is always time equals zero. However, for very large (data) simulations, we can specify a time to start saving data, tstart. The tmax parameter is used to specify the maximum step size. If the plots start to look jagged (like a sinewave that isn't smooth), then tmax should be reduced. CMOS Circuit Design, Layout, and Simulation 16 A SPICE transient analysis simulates circuits in the time domain (as in an oscilloscope, the x-axis is time). Let's simulate, using a transient analysis, the simple circuit seen back in Fig. 1.11. A simulation netlist may look like (see output in Fig. 1.19): Figure 1.19 CMOS: Circuit Design, Layout, and Simulation destroy ail run plot vin vout .tran 100p 100n Vin Vin 0 DC 1 R1 Vin Vout 1k R2 Vout 0 2k .end Figure 1.19 Transient simulation for the circuit in Fig. 1.11. The SIN Source To illustrate a simulation using a sinewave, examine the schematic in Fig 1.20. The statement for a sinewave in SPICE is SIN Vo Va freq td theta The parameter Vo is the sinusoid's offset (the DC voltage in series with the sinewave). The parameter Va is the peak amplitude of the sinewave. Freq is the frequency of the sinewave, while td is the delay before the sinewave starts in the simulation. Finally, theta is used if the amplitude of the sinusoid has a damped nature. Figure 1.20 shows the netlist corresponding to the circuit seen in this figure and the simulation results. 6 Some key things to note in this simulation: (1) MEG is used to specify 10 . Using 3 "m" or "M" indicates milli or 10" . The parameter 1MHz indicates 1 milliHertz. Also, f 15 indicates femto or 10" . A capacitor value of If doesn't indicate one Farad but rather 1 femto Farad. (2) Note how we increased the simulation time to 3 u,s. If we had a simulation time of 100 ns (as in the previous simulation), we wouldn't see much of the sinewave (one-tenth of the sinewave's period). (3) The "SIN" statement is used in a transient simulation analysis. The SIN specification is not used in an AC analysis (discussed later). Chapter 1 Introduction to CMOS Design 17 '"Figure 1.20 Rl,lk Vout destroy all run plot vin vout Vin R2,2k .tran 1n3u IV (peak) at Vin Vin 0 DC 0 SIN 0 1 1MEG 1MHz R1 Vin Vout 1k X7 R2 Vout 0 2k .end Figure 1.20 Simulating a resistive divider with a sinusoidal input. An RC Circuit Example To illustrate the use of a .tran simulation let's determine the output of the RC circuit seen in Fig. 1.21 and compare our hand calculations to simulation results. The output voltage can be written in terms of the input voltage by 1/jeoC 1 or V out — y ih (1.1) 1 +jaRC l/jaC + R V in Taking the magnitude of this equation gives V out (1.2) Jl+(2nßC)2 and taking the phase gives ,271/RC Z - ■ = -tan" (1.3) 1 From the schematic the resistance is Ik, the capacitance is 1 uF, and the frequency is 200 Hz. Plugging these numbers into Eqs. (1.1) - (1.3) gives l-l =0.623 and Zf- = I "in I "in -0.898 radians or -51.5 degrees. With a 1 V peak input then our output voltage is 623 mV (and as seen in Fig. 1.21, it is). Remembering that phase shift is simply an indication of time delay at a particular frequency, Z (radians) = j ■ 2n or Z (degrees) = j ■ 360 = t •/• 360 (1.4) d The way to remember this equation is that the time delay, t is a percentage of the period (7), t IT, multiplied by either 2n (radians) or 360 (degrees). For the present example, the d time delay is 715 us (again, see Fig. 1.21). Note that the minus sign indicates that the output is lagging (occurring later in time) the input (the input leads the output). CMOS Circuit Design, Layout, and Simulation 18 Figure 1.21 Simulating the operation of an RC circuit using a .tran analysis. Another RC Circuit Example As one more example of simulating the operation of an RC circuit consider the circuit seen in Fig. 1.22. Combining the impedances of Cl and R, we get R/jcaCi R = y R+l/jaCi l+jaRCi ' ' The transfer function for this circuit is then V _ l//coC _ 1 +juRC om 2 l (1.6) V I/700C2 + Z 1 +JGR(Ci + C ) in 2 The magnitude of this transfer function is \+(2nJRCif (1.7) 2 11+ (271/7? -(Ci+C )) 2 and the phase response is -■w j (18) 'in t 1 Plugging in the numbers from the schematic gives a magnitude response of 0.6 (which matches the simulation results) and a phase shift of- 0.119 radians or - 6.82 degrees. The amount of time the output is lagging the input is then 682 = Z = - = - =-95us (1.9) td d R V 360 /• 360 200 • 360 ' which is confirmed with the simulation results seen in Fig. 1.22. Chapter 1 Introduction to CMOS Design 19 Figure 1.22 Another RC circuit example. AC Analysis When performing a transient analysis (.tran) the x-axis is time. We can determine the frequency response of a circuit (the x-axis is frequency) using an AC analysis (.ac). An AC analysis is specified in SPICE using .ac dec nd fstart fstop The dec indicates that the x-axis should be plotted in decades. We could replace dec with lin (linear plot on the x-axis) or oct (octave). The term nd indicates the number of points per decade (say 100), while fstart and fstop indicate the start and stop frequencies (note that fstart cannot be zero, or DC, since this isn't an AC signal). The netlist used to simulate the AC response of the circuit in Fig. 1.21 follows. The simulation output is seen in Fig. 1.23, where we've pointed out the response at 200 Hz (the frequency used in Fig. 1.21 and used for calculations on page 17). Figure 1.23 CMOS: Circuit Design, Layout, and Simulation destroy all run plot db(vout/vin) set units=degrees plot ph(vout/vin) .ac dec 1001 10k Vin Vin 0 DC 0 SIN 0 1 200 AC 1 R1 Vin Vout 1k CL Vout 0 1u .end 20 CMOS Circuit Design, Layout, and Simulation Figure 1.23 AC simulation for the RC circuit in Fig. 1.21. Note in this netlist that the SIN specification in Vin has nothing to do with an AC analysis (it's ignored for an AC analysis). For the AC analysis, we added, to the statement for Vin, the term AC 1 (specifying that the magnitude or peak of the AC signal is 1). We can add a phase shift of 45 degrees by using AC 1 45 in the statement. Decades and Octaves In the simulation results seen in Fig. 1.23 we used decades. When we talk about decades we either are multiplying or dividing by 10. One decade above 23 MHz is 230 MHz, while one decade below 1.2 kHz is 120 Hz. When we talk about octaves, we talk about either multiplying or dividing by 2. One octave above 23 MHz is 46 MHz while one octave below 1.2 kHz is 600 Hz. Two octaves above 23 MHz is (multiply by 4) 92 MHz. Decibels When the magnitude response of a transfer function decreases by 10, it is said it goes down by -20 dB (divide by 10, 20-log(0.1) = -20iß). When the magnitude response increases by 10, it goes up by 20 dB (multiply by 10). For the frequency response in Fig. 1.23 (above 159 Hz, the - 3 dB frequency, or here when the magnitude response is 0.707), the response is rolling off at -20 dB/decade. What this means is that if we increase the frequency by 10 the magnitude response decreases by 10. We could also say the response is rolling off at -6 dB/octave above 159 Hz (for every increase in frequency by 2 the magnitude response drops by a factor of 2). If a magnitude response is rolling off at -40 dB/decade, then for every increase in frequency by 10 the magnitude drops by 100. Similarly if a response rolls off at -12 dB/octave, for every doubling in frequency our response drops by 4. Note that - 6 dB/octave is the same rate as -20 dB/decade.

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