Microprocessor and Microcontroller Lecture Notes

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COURSE MATERIAL Subject Code : EC6504 Subject : Microprocessor and Microcontroller Class : III Year ECE Dept. of ECEEC6504 MICROPROCESSOR AND MICROCONTROLLERS S.NO CONTENTS PAGE.NO UNIT–1 THE 8086 MICROPROCESSOR 1 to 40 1.1 Introduction to 8086 1 1.2 Microprocessor architecture 1 1.3 Addressing modes 6 1.4 Instruction set and assembler directives 10 1.5 Assembly language programming 26 1.6 Modular programming 28 1.7 Linking and Relocation 29 1.8 Stacks 32 1.9 Procedures 33 1.1 Macros 34 1.11 Interrupts and interrupt service routines 35 1.12 Byte and String Manipulation 40 UNIT–2 8086 SYSTEM BUS STRUCTURE 41-64 2.1 8086 signals 41 2.2 Basic configurations 46 2.3 System bus timin 47 2.4 System design using 8086 49 2.5 IO programming 51 2.6 Introduction to Multiprogramming 53 2.7 System Bus Structure 53 2.8 Multiprocessor configurations 53 2.9 Coprocessor 54 2.1 Closely coupled and loosely Coupled configurations 56 2.11 Introduction to advanced processors 58 Dept. of ECEEC6504 MICROPROCESSOR AND MICROCONTROLLERS UNIT–3 I/O INTERFACING 65 to 103 3.1 Memory Interfacing and I/O interfacing 65 3.2 Parallel communication interface 70 3.3 Serial communication interface 74 3.4 D/A and A/D Interface 79 3.5 Timer 82 3.6 Keyboard /display controller 88 3.7 Interrupt controller 95 3.8 DMA controller 98 3.9 Traffic Light control 103 UNIT–4 MICROCONTROLLER 104 to 117 4.1 Architecture of 8051 104 4.2 Special Function Registers(SFRs) 107 4.3 I/O Pins Ports and Circuits 110 4.4 Instruction set 113 4.5 Addressing modes 116 4.6 Assembly language programming. 117 UNIT V INTERFACING MICROCONTROLLER 118 to 134 5.1 Programming 8051 Timers 118 5.2 Serial Port Programming 121 5.3 Interrupts Programming 124 5.4 LCD & Keyboard Interfacing 128 5.5 ADC, DAC & Sensor Interfacing 129 5.6 External Memory Interface 131 5.4 Stepper Motor and Waveform generation. 132 Dept. of ECEEC6504 MICROPROCESSOR AND MICROCONTROLLERS EC6504 MICROPROCESSOR AND MICROCONTROLLER L T P C 3 0 0 3 OBJECTIVES: The student should be made to: � Study the Architecture of 8086 microprocessor. � Learn the design aspects of I/O and Memory Interfacing circuits. � Study about communication and bus interfacing. � Study the Architecture of 8051 microcontroller. UNIT I THE 8086 MICROPROCESSOR 9 Introduction to 8086 – Microprocessor architecture – Addressing modes - Instruction set and assembler directives – Assembly language programming – Modular Programming - Linking and Relocation - Stacks - Procedures – Macros – Interrupts and interrupt service routines – Byte and String Manipulation. UNIT II 8086 SYSTEM BUS STRUCTURE 9 8086 signals – Basic configurations – System bus timing –System design using 8086 – IO programming – Introduction to Multiprogramming – System Bus Structure – Multiprocessor configurations – Coprocessor, Closely coupled and loosely Coupled configurations – Introduction to advanced processors. UNIT III I/O INTERFACING 9 Memory Interfacing and I/O interfacing - Parallel communication interface – Serial communication interface – D/A and A/D Interface - Timer – Keyboard /display controller – Interrupt controller – DMA controller – Programming and applications Case studies: Traffic Light control, LED display , LCD display, Keyboard display interface and Alarm Controller. UNIT IV MICROCONTROLLER 9 Architecture of 8051 – Special Function Registers(SFRs) - I/O Pins Ports and Circuits - Instruction set - Addressing modes - Assembly language programming. UNIT V INTERFACING MICROCONTROLLER 9 Programming 8051 Timers - Serial Port Programming - Interrupts Programming – LCD & Keyboard Interfacing - ADC, DAC & Sensor Interfacing - External Memory Interface- Stepper Motor and Waveform generation. 45 PERIODS OUTCOMES: At the end of the course, the student should be able to: � Design and implement programs on 8086 microprocessor. � Design I/O circuits. � Design Memory Interfacing circuits. � Design and implement 8051 microcontroller based systems. TEXT BOOKS: 1.Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088 Family - Architecture, Programming and Design”, Second Edition, Prentice Hall of India, 2007. 2. Mohamed Ali Mazidi, Janice Gillispie Mazidi, Rolin McKinlay, “The 8051 Microcontroller and Embedded Systems: Using Assembly and C”, Second Edition, Pearson Education, 2011 REFERENCE: 1. Doughlas V.Hall, “Microprocessors and Interfacing, Programming and Hardware:,TMH, 2012 Dept. of ECEEC6504 MICROPROCESSOR & MICROCONTROLLER UNIT – I THE 8086 MICROPROCESSOR 1.1 INTRODUCTION · It is a semiconductor device consisting of electronic logic circuits manufactured by using either a Large scale (LSI) or Very Large Scale (VLSI) Integration Technique. · It includes the ALU, register arrays and control circuits on a single chip. The microprocessor has a set of instructions, designed internally, to manipulate data and communicate with peripherals. · The era microprocessors in the year 1971, the Intel introduced the first 4-bit microprocessor is 4004. Using this the first portable calculator is designed. · The 16-bit Microprocessor families are designed primarily to complete with microcomputers and are oriented towards high-level languages. They have powerful instruction sets and capable of addressing mega bytes of memory. · The era of 16-bit Microprocessors began in 1974 with the introduction of PACE chip by National Semiconductor. The Texas Instruments TMS9900 was introduced in the year 1976. The Intel 8086 commercially available in the year 1978, Zilog Z800 in the year 1979, The Motorola MC68000 in the year 1980. · The 16-bit Microprocessors are available in different pin packages. Ex: Intel 8086/8088 40 pin package Zilog Z8001 40 pin package, Digital equipment LSI-II 40 pin package, Motorola MC68000 64 pin package National Semiconductor NS16000 48 pin package. · The primary objectives of this 16-bit Microprocessor can be summarized as follows. 1. Increase memory addressing capability 2. Increase execution speed 3. Provide a powerful instruction set 4. Facilitate programming in high-level languages. 1.2 Microprocessor Architecture: · The 8086 CPU is divided into two independent functional parts, the Bus interface unit (BIU) and execution unit (EU). The Bus Interface Unit contains Bus Interface Logic, Segment registers, Memory addressing logic and a Six byte instruction object code queue. The BIU sends out address, fetches the instructions from memory, read data from ports and memory, and writes the data to ports and memory. · The execution unit: contains the Data and Address registers, the Arithmetic and Logic Unit, the Control Unit and flags. tells the BIU where to fetch instructions or data from, decodes instructions and executes instruction. The EU contains control circuitry which directs internal operations. A decoder in the EU translates instructions fetched from memory into a series of actions which the EU carries out. The EU is has a 16-bit ALU which can add, subtract, AND, OR, XOR, increment, decrement, complement or shift binary numbers. The EU is decoding an instruction or executing an instruction which does not require use of the buses. In other words the BIU handles all transfers of data and addresses on the buses for the execution unit. · The Queue: The BIU fetches up to 6 instruction bytes for the following instructions. The BIU stores these prefetched bytes in first-in-first-out register set called a queue. When the EU is ready for its next instruction it simply reads the instruction byte(s) for the instruction from the queue in the BIU. This is much faster than sending out an address to the system memory and waiting for memory to send back the next instruction byte or bytes. . 1 DEPT. OF ECEEC6504 MICROPROCESSOR & MICROCONTROLLER Fig.1.1 8086 Architecture 2 DEPT. OF ECEEC6504 MICROPROCESSOR & MICROCONTROLLER Except in the case of JMP and CALL instructions, where the queue must be dumped and then reloaded starting from a new address, this prefetch-and-queue scheme greatly speeds up processing. Fetching the next instruction while the current instruction executes is called pipelining. · Word Read: Each of 1 MB memory address of 8086 represents a byte wide location.16-bit words will be stored in two consecutive memory locations. If first byte of the data is stored at an even address, 8086 can read the entire word in one operation. For example if the 16 bit data is stored at even address 00520H is 9634H MOV BX, 00520H 8086 reads the first byte and stores the data in BL and reads the 2nd byte and stores the data in BH BL= (00520H) i.e. BL=34H BH= (00521H) BH=96H If the first byte of the data is stored at an odd address, 8086 needs two operations to read the 16 bit data. For example if the 16 bit data is stored at even address 00521H is 3897H MOV BX, 00521H In first operation, 8086 reads the 16 bit data from the 00520H location and stores the nd data of 00521H location in register BL and discards the data of 00520H location In 2 operation, 8086 reads the 16 bit data from the 00522H location and stores the data of 00522H location in register BH and discards the data of 00523H location. BL= (00521H) i.e. BL=97H BH= (00522H) BH=38H · Byte Read: MOV BH, Addr For Even Address: Ex: MOV BH, 00520H 8086 reads the first byte from 00520 location and stores the data in BH and reads the nd 2 byte from the 00521H location and ignores it BH = 00520H For Odd Address MOV BH, Addr Ex: MOV BH, 00521H 8086 reads the first byte from 00520H location and ignores it and reads the 2nd byte from the 00521 location and stores the data in BH BH = 00521H · Physical address formation: The 8086 addresses a segmented memory. The complete physical address which is 20- bits long is generated using segment and offset registers each of the size 16-bit.The content of a segment register also called as segment address, and content of an offset register also called as offset address. To get total physical address, put the lower nibble 0H to segment address and add offset address. The fig 1.3 shows formation of 20-bit physical address. 3 DEPT.OF ECEEC6504 MICROPROCESSOR & MICROCONTROLLER Fig 1.2 Physical Adress formation . · Register organization of 8086: All the registers of 8086 are 16-bit registers. The general purpose registers, can be used either 8-bit registers or 16-bit registers used for holding the data, variables and intermediate results temporarily or for other purpose like counter or for storing offset address for some particular addressing modes etc. The special purpose registers are used as segment registers, pointers, index registers or as offset storage registers for particular addressing modes. Fig 1.3 Fig 1.3 Register organization of 8086  AX Register: Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16- bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations, rotate and string manipulation.  BX Register: This register is mainly used as a base register. It holds the starting base location of a memory region within a data segment. It is used as offset storage for forming physical address in case of certain addressing mode.  CX Register: It is used as default counter - count register in case of string and loop instructions.  DX Register: Data register can be used as a port number in I/O operations and implicit operand or destination in case of few instructions. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number. Segment registers: 1Mbyte memory is divided into 16 logical segments. The complete 1Mbyte memory segmentation is as shown in fig 1.4. Each segment contains 64Kbyte of memory. There are four segment registers.  Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. 4 DEPT.OF ECEEC6504 MICROPROCESSOR & MICROCONTROLLER The CS register is automatically updated during far jump, far call and far return instructions. It is used for addressing a memory location in the code segment of the memory, where the executable program is stored.  Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction. It is used for addressing stack segment of memory. The stack segment is that segment of memory, which is used to store stack data.  Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions. It points to the data segment memory where the data is resided.  Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions. It also refers to segment which essentially is another data segment of the memory.  It also contains data. Fig1.4. Memory segmentation  Pointers and index registers. The pointers contain within the particular segments. The pointers IP, BP, SP usually contain offsets within the code, data and stack segments respectively Stack Pointer (SP) is a 16-bit register pointing to program stack in stack segment. Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing. Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data addresses in string manipulation instructions. 5 DEPT.OF ECEEC6504 MICROPROCESSOR & MICROCONTROLLER Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions.  Flag Register: Fig. 1.5 Flag Register Flags Register determines the current state of the processor. They are modified automatically by CPU after mathematical operations, this allows to determine the type of the result, and to determine conditions to transfer control to other parts of the program. The 8086 flag register as shown in the fig 1.5. 8086 has 9 active flags and they are divided into two categories: 1. Conditional Flags 2. Control Flags  Conditional Flags Carry Flag (CY): This flag indicates an overflow condition for unsigned integer arithmetic. It is also used in multiple-precision arithmetic. Auxiliary Flag (AC): If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AC flag is set i.e. carry given by D3 bit to D4 is AC flag. This is not a general-purpose flag, it is used internally by the Processor to perform Binary to BCD conversion. Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity flag is reset. Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset. Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation is negative, sign flag is set.  Control Flags Control flags are set or reset deliberately to control the operations of the execution unit. Control flags are as follows: Trap Flag (TF): It is used for single step control. It allows user to execute one instruction of a program at a time for debugging. When trap flag is set, program can be run in single step mode. Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is disabled. It can be set by executing instruction sit and can be cleared by executing CLI instruction. Direction Flag (DF): It is used in string operation. If it is set, string bytes are accessed from higher memory address to lower memory address. When it is reset, the string bytes are accessed from lower memory address to higher memory address. 1.3 Addressing Modes The 8086 has 12 addressing modes can be classified into five groups. · Addressing modes for accessing immediate and register data (register and immediate modes). · Addressing modes for accessing data in memory (memory modes) 6 DEPT.OF ECEEC6504 MICROPROCESSOR & MICROCONTROLLER · Addressing modes for accessing I/O ports (I/O modes) · Relative addressing mode · Implied addressing mode  Immediate addressing mode: In this mode, 8 or 16 bit data can be specified as part of the instruction - OP Code Immediate Operand Example 1: MOV CL, 03 H:Moves the 8 bit data 03 H into CL Example 2: MOV DX, 0525 H: Moves the 16 bit data 0525 H into DX In the above two examples, the source operand is in immediate mode and the destination operand is in register mode. A constant such as “VALUE” can be defined by the assembler EQUATE directive such as VALUE EQU 35H Example: MOV BH, VALUE Used to load 35 H into BH  Register addressing mode: The operand to be accessed is specified as residing in an internal register of 8086. Table 1.1 below shows internal registers, anyone can be used as a source or destination operand, however only the data registers can be accessed as either a byte or word. Table 1.1 Internal registers of 8086 Example 1: MOV DX (Destination Register) , CX (Source Register) Which moves 16 bit content of CS into DX. Example 2: MOV CL, DL Moves 8 bit contents of DL into CL MOV BX, CH is an illegal instruction. The register sizes must be the same.  Direct addressing mode: The instruction Opcode is followed by an affective address, this effective address is directly used as the 16 bit offset of the storage location of the operand from the location specified by the current value in the selected segment register. The default segment is always DS. The 20 bit physical address of the operand in memory is normally obtained as PA = DS: EA 7 DEPT.OF ECEEC6504 MICROPROCESSOR & MICROCONTROLLER But by using a segment override prefix (SOP) in the instruction, any of the four segment registers can be referenced, Fig 1.6 Physical address generation of 8086 The Execution Unit (EU) has direct access to all registers and data for register and immediate operands. However the EU cannot directly access the memory operands. It must use the BIU, in order to access memory operands. In the direct addressing mode, the 16 bit effective address (EA) is taken directly from the displacement field of the instruction. Example 1: MOV CX, START If the 16 bit value assigned to the offset START by the programmer using an assembler pseudo instruction such as DW is 0040 and DS = 3050. Then BIU generates the 20 bit physical address 30540 H. The content of 30540 is moved to CL The content of 30541 is moved to CH Example 2: MOV CH, START If DS = 3050 and START = 0040 8 bit content of memory location 30540 is moved to CH. Example 3: MOV START, BX With DS = 3050, the value of START is 0040. Physical address: 30540 MOV instruction moves (BL) and (BH) to locations 30540 and 30541 respectively.  Register indirect addressing mode: The EA is specified in either pointer (BX) register or an index (SI or DI) register. The 20 bit physical address is computed using DS and EA. Example: MOV DI, BX register indirect If DS = 5004, DI = 0020, Bx = 2456 PA=50060. The content of BX(2456) is moved to memory locations 50060 H and 50061 H. when memory is accessed PA is computed from BX and DS when the stack is accessed PA is computed from BP and SS. Example: MOV AL, START BX or MOV AL, START + BX based mode 8 DEPT.OF ECEEC6504 MICROPROCESSOR & MICROCONTROLLER EA: START + BX PA: DS + EA The 8 bit content of this memory location is moved to AL.  String addressing mode: The string instructions automatically assume SI to point to the first byte or word of the source operand and DI to point to the first byte or word of the destination operand. The contents of SI and DI are automatically incremented (by clearing DF to 0 by CLD instruction) to point to the next byte or word. Example: MOV S BYTE If DF = 0, DS = 2000 H, SI = 0500, ES = 4000, DI = 0300 Source address: 20500, assume it contains 38 PA: DS + SI Destination address: ES + DI = 40300, assume it contains 45  I/O mode (direct): Port number is an 8 bit immediate operand. Example: OUT 05 H, AL Outputs AL to 8 bit port 05 H I/O mode (indirect): The port number is taken from DX. Example 1: IN AL, DX If DX = 5040 8 bit content by port 5040 is moved into AL. Example 2: IN AX, DX Inputs 8 bit content of ports 5040 and 5041 into AL and AH respectively.  Relative addressing mode: Example: JNC START 9 DEPT.OF ECEEC6504 MICROPROCESSOR & MICROCONTROLLER If CY=O, then PC is loaded with current PC contents plus 8 bit signed value of START, otherwise the next instruction is executed.  Implied addressing mode: Instruction using this mode have no operands. Example: CLC which clears carry flag to zero. Fig 1.7 Summary of 8086 addressing modes 1.4 INSTRUCTION SET OF 8086 The 8086 instructions are categorized into the following main types. 1. Data Copy / Transfer Instructions 2. Arithmetic and Logical Instructions 3. Shift and Rotate Instructions 4. Loop Instructions 5. Branch Instructions 6. String Instructions 7. Flag Manipulation Instructions 8. Machine Control Instructions 1.4.1 Data Copy / Transfer Instructions: MOV: 10 DEPT.OF ECEEC6504 MICROPROCESSOR & MICROCONTROLLER This instruction copies a word or a byte of data from some source to a destination. The destination can be a register or a memory location. The source can be a register, a memory location, or an immediate number. MOV AX, BX MOV AX, 5000H MOV AX, SI MOV AX, 2000H MOV AX, 50HBX MOV 734AH, BX MOV DS, CX MOV CL, 357AH Direct loading of the segment registers with immediate data is not permitted. PUSH: Push to Stack This instruction pushes the contents of the specified register/memory location on to the stack. The stack pointer is decremented by 2, after each execution of the instruction. E.g. PUSH AX • PUSH DS • PUSH 5000H POP: Pop from Stack This instruction when executed, loads the specified register/memory location with the contents of the memory location of which the address is formed using the current stack segment and stack pointer. The stack pointer is incremented by 2 Eg. POP AX POP DS POP 5000H Fig 1.8 Push into and Popping Register Content from Stack Memory XCHG: Exchange byte or word This instruction exchange the contents of the specified source and destination operands Eg. XCHG 5000H, AX 11 DEPT.OF ECEEC6504 MICROPROCESSOR & MICROCONTROLLER XCHG BX, AX XLAT: Translate byte using look-up table Eg. LEA BX, TABLE1 MOV AL, 04H XLAT Input and output port transfer instructions: IN: Copy a byte or word from specified port to accumulator. Eg. IN AL,03H IN AX,DX OUT: Copy a byte or word from accumulator specified port. Eg. OUT 03H, AL OUT DX, AX LEA: Load effective address of operand in specified register. reg offset portion of address in DS Eg. LEA reg, offset LDS: Load DS register and other specified register from memory. reg mem DS mem + 2 Eg. LDS reg, mem LES: Load ES register and other specified register from memory. reg mem ES mem + 2 Eg. LES reg, mem Flag transfer instructions: LAHF: Load (copy to) AH with the low byte the flag register. AH Flags low byte Eg. LAHF SAHF: Store (copy) AH register to low byte of flag register. Flags low byte AH Eg. SAHF PUSHF: Copy flag register to top of stack. SP SP – 2 SP Flags Eg. PUSHF POPF: Copy word at top of stack to flag register. Flags SP SP SP + 2 1.4.2 Arithmetic Instructions: 12 DEPT.OF ECEEC6504 MICROPROCESSOR & MICROCONTROLLER The 8086 provides many arithmetic operations: addition, subtraction, negation, multiplication and comparing two values. ADD: The add instruction adds the contents of the source operand to the destination operand. Eg. ADD AX, 0100H ADD AX, BX ADD AX, SI ADD AX, 5000H ADD 5000H, 0100H ADD 0100H ADC: Add with Carry This instruction performs the same operation as ADD instruction, but adds the carry flag to the result. Eg. ADC 0100H ADC AX, BX ADC AX, SI ADC AX, 5000 ADC 5000, 0100H SUB: Subtract The subtract instruction subtracts the source operand from the destination operand and the result is left in the destination operand. Eg. SUB AX, 0100H SUB AX, BX SUB AX, 5000H SUB 5000H, 0100H SBB: Subtract with Borrow The subtract with borrow instruction subtracts the source operand and the borrow flag (CF) which may reflect the result of the previous calculations, from the destination operand Eg. SBB AX, 0100H SBB AX, BX SBB AX, 5000H SBB 5000H, 0100H INC: Increment This instruction increases the contents of the specified Register or memory location by 1. Immediate data cannot be operand of this instruction. Eg. INC AX INC BX INC 5000H DEC: Decrement The decrement instruction subtracts 1 from the contents of the specified register or memory location. Eg. DEC AX DEC 5000H NEG: Negate The negate instruction forms 2’s complement of the specified destination in the instruction. The destination can be a register or a memory location. This instruction can be implemented by inverting each bit and adding 1 to it. Eg. NEG AL AL = 0011 0101 35H Replace number in AL with its 2’s complement AL = 1100 1011 = CBH 13 DEPT.OF ECEEC6504 MICROPROCESSOR & MICROCONTROLLER CMP: Compare This instruction compares the source operand, which may be a register or an immediate data or a memory location, with a destination operand that may be a register or a memory location Eg. CMP BX, 0100H CMP AX, 0100H CMP 5000H, 0100H CMP BX, SI CMP BX, CX MUL:Unsigned Multiplication Byte or Word This instruction multiplies an unsigned byte or word by the contents of AL. Eg. MUL BH; (AX) (AL) x (BH) MUL CX; (DX)(AX) (AX) x (CX) MUL WORD PTR SI; (DX)(AX) (AX) x (SI) IMUL:Signed Multiplication This instruction multiplies a signed byte in source operand by a signed byte in AL or a signed word in source operand by a signed word in AX. Eg. IMUL BH IMUL CX IMUL SI CBW: Convert Signed Byte to Word This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to be sign extension of AL. Eg. CBW AX= 0000 0000 1001 1000 Convert signed byte in AL signed word in AX. Result in AX = 1111 1111 1001 1000 CWD: Convert Signed Word to Double Word This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to be sign extension of AL. Eg. CWD Convert signed word in AX to signed double word in DX: AX DX= 1111 1111 1111 1111 Result in AX = 1111 0000 1100 0001 DIV: Unsigned division This instruction is used to divide an unsigned word by a byte or to divide an unsigned double word by a word. Eg. DIV CL; Word in AX / byte in CL; Quotient in AL, remainder in AH DIV CX; Double word in DX and AX / word; in CX, and Quotient in AX; remainder in DX AAA: ASCII Adjust After Addition The AAA instruction is executed after an ADD instruction that adds two ASCII coded operand to give a byte of result in AL. The AAA instruction converts the resulting contents of Al to a unpacked decimal digits. Eg. ADD CL, DL; CL = 32H = ASCII for 2; DL = 35H = ASCII for 5; Result CL = 67H MOV AL, CL; Move ASCII result into AL since; AAA adjust only AL AAA; AL=07, unpacked BCD for 7 AAS: ASCII Adjust AL after Subtraction This instruction corrects the result in AL register after subtracting two unpacked ASCII operands. The result is in unpacked decimal format. The procedure is similar to AAA instruction except for the subtraction of 06 from AL. AAM: ASCII Adjust after Multiplication 14 DEPT.OF ECEEC6504 MICROPROCESSOR & MICROCONTROLLER This instruction, after execution, converts the product available In AL into unpacked BCD format. Eg. MOV AL, 04; AL = 04 MOV BL ,09; BL = 09 MUL BL; AX = ALBL; AX=24H AAM; AH = 03, AL=06 AAD: ASCII Adjust before Division This instruction converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL. This adjustment must be made before dividing the two unpacked BCD digits in AX by an unpacked BCD byte. In the instruction sequence, this instruction appears Before DIV instruction. Eg. AX 05 08 AAD result in AL 00 3A 58D = 3A H in AL The result of AAD execution will give the hexadecimal number 3A in AL and 00 in AH where 3A is the hexadecimal Equivalent of 58 (decimal). DAA: Decimal Adjust Accumulator This instruction is used to convert the result of the addition of two packed BCD numbers to a valid BCD number. The result has to be only in AL. Eg. AL = 53 CL = 29 ADD AL, CL; AL (AL) + (CL); AL 53 + 29; AL 7C DAA; AL 7C + 06 (as C9); AL 82 DAS: Decimal Adjust after Subtraction This instruction converts the result of the subtraction of two packed BCD numbers to a valid BCD number. The subtraction has to be in AL only. Eg. AL = 75, BH = 46 SUB AL, BH; AL 2 F = (AL) - (BH) ; AF = 1 DAS; AL 2 9 (as F9, F - 6 = 9) Logical instructions AND: Logical AND This instruction bit by bit ANDs the source operand that may be an immediate register or a memory location to the destination operand that may a register or a memory location. The result is stored in the destination operand. Eg. AND AX, 0008H AND AX, BX OR: Logical OR This instruction bit by bit ORs the source operand that may be an immediate, register or a memory location to the destination operand that may a register or a memory location. The result is stored in the destination operand. Eg. OR AX, 0008H OR AX, BX NOT: Logical Invert This instruction complements the contents of an operand register or a memory location, bit by bit. Eg. NOT AX NOT 5000H OR: Logical Exclusive OR 15 DEPT.OF ECEEC6504 MICROPROCESSOR & MICROCONTROLLER This instruction bit by bit XORs the source operand that may be an immediate, register or a memory location to the destination operand that may a register or a memory location. The result is stored in the destination operand. Eg. XOR AX, 0098H XOR AX, BX TEST: Logical Compare Instruction The TEST instruction performs a bit by bit logical AND operation on the two operands. The result of this ANDing operation is not available for further use, but flags are affected. Eg. TEST AX, BX TEST 0500, 06H 1.4. 3 Shift and Rotate Instructions SAL/SHL: SAL / SHL destination, count. SAL and SHL are two mnemonics for the same instruction. This instruction shifts each bit in the specified destination to the left and 0 is stored at LSB position. The MSB is shifted into the carry flag. The destination can be a byte or a word. It can be in a register or in a memory location. The number of shifts is indicated by count. Eg. SAL CX, 1 SAL AX, CL SHR: SHR destination, count This instruction shifts each bit in the specified destination to the right and 0 is stored at MSB position. The LSB is shifted into the carry flag. The destination can be a byte or a word. It can be a register or in a memory location. The number of shifts is indicated by count. Eg. SHR CX, 1 MOV CL, 05H SHR AX, CL SAR: SAR destination, count This instruction shifts each bit in the specified destination some number of bit positions to the right. As a bit is shifted out of the MSB position, a copy of the old MSB is put in the MSB position. The LSB will be shifted into CF. Eg. SAR BL, 1 MOV CL, 04H SAR DX, CL ROL Instruction: ROL destination, count This instruction rotates all bits in a specified byte or word to the left some number of bit positions. MSB is placed as a new LSB and a new CF. Eg. ROL CX, 1 MOV CL, 03H ROL BL, CL ROR Instruction: ROR destination, count This instruction rotates all bits in a specified byte or word to the right some number of bit positions. LSB is placed as a new MSB and a new CF. Eg. ROR CX, 1 MOV CL, 03H ROR BL, CL RCL Instruction: RCL destination, count This instruction rotates all bits in a specified byte or word some number of bit positions to the left along with the carry flag. MSB is placed as a new carry and previous carry is place as new LSB. Eg. RCL CX, 1 MOV CL, 04H 16 DEPT.OF ECE

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