Applications of Microprocessor

Applications of Microprocessor
Dr.NaveenBansal Profile Pic
Published Date:25-10-2017
Your Website URL(Optional)
14 Serial Communication and Programmable Communication Interface In continuation to the series of interfacing devices, the discussion will now be made on serial data communication and programmable communication interface, since the serial data transmission is always preferred for long distance transmission. Though the serial data transmission can be made through the SID (serial input data) and SOD (serial out data) lines of 8085A microprocessor, but it requires suitable software for the data transfer. Moreover, most of the microprocessors do not have the provision of SID and SOD lines. Apart from this, it can not offer high baud rate. Hence this chapter will deal the detailed discussion on serial communication and most powerful programmable communication interface IC 8251. 14.1 SERIAL DATA COMMUNICATION There are two types of data communication, Parallel and Serial data communications. In parallel data communication each bit of a word is to be transmitted on a separate line along with a common ground line. In the 8085A microprocessor the data to be transmitted is of 8 bits. This parallel data transmission is not recommended for long distance communication as large number of data lines is needed. In serial data transmission, data is transmitted bit by bit either from the microprocessor to I/O devices or vice-versa. There are certain input/output devices in the microprocessor based systems, which only accept the serial data. The common I/O devices for such a data communication are CRT terminals, printers, cassette recorders etc. The microprocessors thus have the provision for transferring the data in the serial fashion. In such I/O devices, a parallel to serial conversion is required for the data transfer from the microprocessor to the peripheral device (figure 14.1a). Similarly, a serial to parallel conversion is required in transmitting the data from the peripheral device to the microprocessor (figure 14.1b). As already discussed, the 8085A microprocessor has the provision of SID and SOD lines for the serial data transfer between the microprocessor and I/O devices. But it requires the software. Moreover, most of the microprocessors do not have the provision of these SID and SOD lines. Apart from this, it can not offer high baud rate. So, serial data communication is generally used for the long distance communication with high baud rate. Further, it requires less number of lines for the data transmission. (a) (b) Fig. 14.1 The serial communication occurs either in the following two formats: • Synchronous • Asynchronous In synchronous format, a receiver and a transmitter are synchronized. In this format the data is divided into fairly large blocks, typically 1000s of bytes. A block of characters is transmitted along with the synchronization information. The synchronizing signals are added once before each block. The synchronization characters mark the beginning of the transmission. This format is generally used for high baud rate (more than 20 K bits/second). The baud rate is defined as the number of bits transmitted or received per second. Figure 14.2 illustrates this format. Fig. 14.2 In asynchronous format, timing signals are added to each character of data. A START bit is added at the beginning of each character. A STOP bit is added at the end of the character data. A low signal is used for the START bit and a high signal is used for STOP bit. When no data is being transmitted, a receiver stays high, called MARK. The process of adding start and stop bits to a character is known as FRAMING. The asynchronous format is generally used for low speed transmission. This format is illustrated in figure 14.3. 424 Fig. 14.3 The serial mode of data transfer can be divided into three groups namely: Simplex Method Duplex Method Half Duplex Method In simplex method data transfer takes place in unidirectional i.e. either from the system to the I/O devices or from I/O devices to the system, of course through the serial link. A typical example is the transmission from a system to a printer. In the duplex method data transfer takes place in both the directions. However, if the transmission goes one way at a time, it is called half duplex; if it goes both ways simultaneously, it is called full duplex. The walkie talkie is an example of half duplex and the communication between the computers is an example of full duplex. 14.2 MODEM One of the most common applications of the serial transmission would be data transmission between large computers. For such serial digital transmission the existing telephone lines are used. The telephone lines are designed to carry analog signals in the range of 40 Hz to 4 KHz. These lines will not readily support digital signals. Therefore, the digital data is to be converted into audio frequency format. A device that can convert the digital value in the form of the audio signal has to be used because the basic binary bits can not be placed directly on these lines. Such a device is known as MODEM (MODULATOR- DEMODULATOR). The modem is be used at both the ends; at the Fig. 14.4 425receiving end as well as at the transmitting end. The modem at the transmitting end converts digital signal into analog signal format (audio frequency range) and at the receiving end the modem converts audio signal back to the digital data. Fig. 14.5 Modems often use frequency shift keying technique for the conversion. It converts a 1 level signal into an audio signal of 1200 HZ and 0 level into audio signal of 2200 Hz. These converted audio signals are modulated on the carrier and then transmitted to the telephone lines. However at the receiving end another modem is used to convert the audio signal back to digital form. Figure 14.4 shows the block diagram of such transmission system. The originators and receptors of the digital data are called Data Terminal Equipments (DTE) and the modem units are called Data Communication Equipments (DCE). Figure 14.5 shows the modem connections using telephone lines. 14.3 SERIAL COMMUNICATION STANDARD There are primarily two standards for transmitting the information in serial form. All the serial I/O devices work on either of these standards. • Current Loop • Voltage standard In a current loop method, the current flows through the lines for the logic 1 and no current flow for the logic 0. The two standards for the current loop are: 20 milliampere loop 60 milliampere loop. A current loop reduces noise pickup and is suitable for long distance transmission. The other standard is the voltage signal. When the data is transmitted as voltage, the commonly used standard is known as RS 232C. It is defined in reference to DTE (Data Terminal Equipment) and DCE (Data Communication Equipment) – terminal and Modem as shown in figure 14.6, which illustrates the connections of DTE to DCE. This standard was developed before the existence of TTL logics; its voltage levels are not compatible with TTL logic levels. 426 Fig. 14.6 RS 232C Figure 14.7 shows the RS 232C 25-pin connector. The signals are divided into four groups namely: • Data Signals • Control Signals • Timing Signals • Ground Fig. 14.7 The pin assignments are given below: Pin 1: Protective Ground Pin 2: Transmitted Data (T x D) DCE Pin 3: Received Data (R x D) DTE Pin 4: Request to Send (RTS) DCE Pin 5: Clear to Send (CTS) DTE Pin 6: Data Set Ready DTE Pin 7: Signal Ground Pin 8: Received Line Signal Detector Pin 9: Reserved for Data Set Testing Pin 10: Reserved for Data Set Testing Pin 11: Unused Pin 12: Secondary Received Line Signal Detector Pin 13: Secondary Clear to send Pin 14: Secondary Transmitted Data Pin15: Transmission Signal Element Timing (DCE Source) 427Pin 16: Secondary Received Data Pin 17: Receiver Signal Element Timing (DCE Source) Pin 18: Unused Pin 19: Secondary Request to Send Pin 20: DCE Data Terminal Ready (DTR) Pin 21: Signal Quality Detector Pin 22: Ring Indicator Pin 23: Data Signal Rate Selector (DTE/DCE Source) Pin 24: Transmit Signal Element Timing (DTE Source) Pin 25: Unused Technically the RS232C has -3V to -12V for logic '1' and +3V to +12V for logic '0'. This is negative logic. Because of incompatibility with TTL logic, voltage translator called line drivers and line receivers are required to interface TTL logic with RS232 signals. As shown in figure 14.6, the minimum interface requires three lines: pins 2, 3 and 7. These lines are defined in relation to the DTE; the terminal transmits on pin 2 and receives on pin 3. On the other hand, the DCE transmits on pin 3 and receives on pin 2. The comparative study of synchronous and Asynchronous modes of data transfer to and from the serial I/O devices is given in table 14.1. Table 14.1 Serial Transmission Sr. Format Synchronous Asynchronous No. 1. Data format One character at a time. Groups of characters 2. Framing START and STOP bit/bits Synchronous characters are are sent with each character. sent with each group. Low, Less than 20 K bits/sec. High speed, 20 K bits/sec 3. Speed or more. Recommended for long Recommended for small 4. Distance for distance communication. distance communication. communication. Hardware. Hardware or Software. Implementation 5. Simplex, half and full Simplex, half and full Data direction 6. duplex. duplex. 428 The computer communicates with the serial I/O devices either in Asynchronous or Synchronous modes. Here the discussion will be made on the Asynchronous mode of serial data transfer, as it is both hardware and software implemented. 14.4 ASYNCHRONOUS SOFTWARE APPROACH In this case, the framing of each character is done by introducing START and STOP bits using the software. The data in parallel form is available with the microprocessor to be transmitted to serial I/O devices. The data is then converted to serial form using the software and sent to the serial I/O devices through an interfacing circuit. The interfacing circuit is to be designed for the microprocessor 8085A microprocessor is shown in figure 14.8. This circuit consists of D-type flip-flop (IC 7475) whose device address is chosen to be FF H. The address bus is decoded using an 8-inpout NAND gate (IC 7430), and combined with the control signal IOW to clock the latch. When the instruction OUT FF H is executed, the clock goes high and bit at the D terminal is IN transferred to output Q of the flip-flop. The bit is latched as the clock goes low. If the Q is high 20 mA current flows through the TTY (Tele Type) circuit. Fig. 14.8 Let us consider, a message is to be transmitted to teletype (TTY) using the 8085A microprocessor. The interfacing circuit, shown in figure 14.8, is used for this transmission. The characters of the message are stored in the memory locations starting at 2101 H. Each character includes framing information (START and STOP bits). Each character has 11 bits for the transmission; 8 bits for ASCII character, one START bit and two STOP bits. .Let the first character of the message is W (ASCII code for W is 57 H). Figure 14.9 shows a stream of eleven bits for this first ASCII character of the message. The character bits are transmitted beginning with the least significant bit (LSB) D . The 0 429bit time, the delay between two successive bits, is determined by the transmission rate (baud rate). Fig. 14.9 A typical (TTY) sends (or receives) 10 ASCII characters per second. If each character has 11 bits, then TTY transmits 110 bits/second. TTY transmission rate = 110 bits/second 1sec Time for each bit = 110 = 9.1 msec. Therefore, microprocessor should send bit by bit information (including framing bits) to TTY to transmit the bit a time interval of 9.1 msec. For the transmission the necessary software for 8085A is given as: PROGRAM Label Mnemonics Operand Comments LXI SP, XXXX H ; Initialize Stack pointer. LXI H, 2101 H ; Initialize H-L register pair for index pointer. MVI A, 01 H ; Set up MARK bit as 1. OUT FF H ; Goes to the output of Flip-flop, whose address is FF H. NXT MOV A, M ; Accumulator is loaded with the character of the message. CPI 0D H ; Compare if the character is Carriage return (0D H is the ASCII Code of carriage return). MOV B, A ; Save the character in register B. JZ END ; If the character is Carriage return, jump to END. 430 CALL SERIAL ; Else Call subroutine for converting into the serial form of the character. INX H ; Point to next character of the message. JMP NXT ; Jump for next character. END CALL SERIAL ; Call subroutine for converting into the serial form of the character ‘Carriage return’. MVI B, 0A H ; Load the character of Line feed (0A H is the ASCII code for line feed). CALL SERIAL ; Transmit line feed serially. HLT ; Stop Processing. SUBROUTINE PROGRAM: This is the subroutine for the conversion of bit of a character into serial form and then transmits to a TTY with a baud rate of 110. Label Mnemonics Operand Comments SERIAL MVI C, 08 H ; Load register C with 08 H, which is used as counter. MVI A, 00 H ; Load START bit. OUT FF H ; Send the start bit at the output of the flip-flop. CALL DELAY ; Call delay subroutine which introduces a time delay of 9.1 msec after START bit. MOV A, B ; Load the character into the accumulator from register B. NXT1 OUT FF H ; Send the bit. CALL DELAY ; Call delay subroutine which introduces a time delay of 9.1 msec between each bit. RRC ; Rotate right for the serial conversion. DCR C ; Decrement C. JNZ NXT1 ; If rotated 8 times then jump to NXT1. MVI A, 01 H ; Introduce STOP bit. OUT FF H ; STOP is sent to the output of the flip-flop. CALL DELAY ; Call delay subroutine which introduces a time delay of 9.1 msec. 431 CALL DELAY ; Call delay subroutine which introduces a time delay of 9.1 msec. RET ; Go back to main program. Delay Program may be written for the time delay of 9.1 msec. Similar, circuit and software may be used for the reception of the messages in the serial fashion. The RIM and SIM instructions can also be used for the transmission and reception of data in serial fashion. 14.5 PROGRAMMABLE COMMUNICATION INTERFACE Many types of UART (Universal Asynchronous Receiver Transmitter) and USART (Universal Synchronous/Asynchronous Receiver Transmitter) have been developed for data transfer between serial I/O device and the microcomputer in the form of the chips. The USART is most powerful and commonly used LSI chip. It provides a programmable serial communication interface between the microprocessor and serial I/O devices. The data transfer between the microprocessor and USART takes place in the parallel form. On the other hand the data transfer between the I/O devices and the USART is in the serial form. The USART has to be initialized before the data transfer takes place. The desired data format and synchronization method for the data transfer are specified during initialization by command byte written by the microprocessor for the USART. Thus an USART works as parallel to serial converter from microprocessor to I/O devices and vice-versa. Here we shall discuss the details of the popular USART chip 8251. 14.6 BLOCK DIAGRAM OF 8251A The 8251A is a programmable communication interface available in the form of IC dual in line package. It consists of 28 pins and requires + 5 V d.c. supply for its operation. Figure 14.10 shows the pin diagram of 8251A. The pin details are as given below: D -D Data bus (8 bits) RxC Receiver Clock 0 7 C/ D Control or data to RxD Receiver Data be written or read RxRDY Receiver Ready RD Read Data TxRDY Transmitter Ready Command DSR Data Set Ready WR Write Data or DTR Data Terminal Ready Control Command SYNDET/BD Sync/Break Detect CLK Clock Pulse (TTL) RTS Request to Send Data Chip Enable Clear to Send Data CS CTS RESET RESET Input TxE Transmitter Empty Transmitter Clock V + 5 V TxC CC TxD Transmitter Data GND Ground 432 Fig. 14.10 The functional block diagram of 8251A is shown in figure 14.11. It includes the following four sections: • Read/Write Control Logic • Transmitter Section • Receiver Section • Modem Control 14.6.1 Read/Write Control Logic This section includes 6-input signals: CS , C / D , WR , RESET and CLK; and three buffer registers: • Control Register • Status Register • Data Bus Buffer Register CS : It is a Chip Select terminal. A low to this terminal selects the 8251A for communication with the microprocessor. This is connected to a decoded address bus. C / D : It is a Control/Data pin. A high on this terminal addresses the control register or status register; whereas a low addresses the data bus buffer. WR : It is an active low Write signal. When a low signal is applied to this terminal, the microprocessor either writes in the control word register or 433sends output to the data buffer. This pin is connected to either IOW or . MRMW Fig. 14.11 RD : It is an active low Read signal. When this terminal is low, the microprocessor either reads the status from the status register or accepts data from the data buffer. This is connected to either IOR or MEMR . RESET : It is a Reset input pin. When this terminal is high, it resets the 8251 and forces it in the idle mode. CLK : This is the Clock input, usually connected with the system clock. The details of the three registers are as: Control Register: This is a 16-bit register and contains the control word with two independent bytes. The first byte is called the Mode Instruction Word, and the second byte is called the Command Instruction Word. This register can be accessed as an output port when C / D pin is high. Status Register: 434 This input register checks the Ready status of a peripheral. This register is addressed as an input port when terminal is high. It has the same port address as C / D the control register. Data Bus Buffer Register This is a bidirectional register and can be addressed as an input port and an output port when C / D pin is low. Table 14.2 gives the summary of interfacing and control signals. Table 14.2 Functions CS C / D RD WR 0 Microprocessor writes instruction in USART control register. 1 1 0 0 Microprocessor reads from USART status register. 1 0 1 0 Microprocessor outputs data to USART data buffer. 0 1 0 0 0 1 Microprocessor accepts data from USART data buffer. 0 X X X 1 USART not selected. Figure 14.12 shows the expanded version of this section. Fig. 14.12 435 14.6.2 Transmitter Section The expanded block diagram of the transmitter section is shown in figure 14.13. It consists of the following registers: • Transmitter Buffer Register – It holds 8-bit data. • Serial Output Register – Converts 8-bits into a stream of serial bits. • Transmitter Control Logic – It directs the output register to send the serial data at the output register through TxD terminal. Three output signals and one input signal are also associated with the transmitter section. These signals are describes as: : It is Transmit Data terminal. The serial bits are transmitted on this TxD line. TxC : This pin is Transmitter Clock. This controls the rate at which bits are to be transmitted by the 8251A. The clock frequency can be 1, 16 or 64 times of the baud. TxRDY : This is Transmitter Ready pin. When this output terminal is high, it indicates that the buffer is empty and the 8251 is ready to accept a byte. It can be used either to interrupt the microprocessor or to indicate the status. This signal becomes reset when the data byte is loaded into the transmitter buffer register. : This is Transmitter Empty signal used as output terminal. A high TxE on this terminal indicates that the output register is empty and becomes reset when a byte is transferred from the buffer register to the output register. Fig. 14.13 43614.6.3 Receiver Section The expanded block diagram of the receiver section is shown in figure 14.14. It consists of the following registers: • Receiver Buffer Register • Serial Input Register • Receiver Control Logic The receiver section accepts serial data on the RxD terminal and converts it to parallel data. When the RxD line goes low, the control logic assumes that it is a START bit and waits for half a bit time, and samples the line again. It the line is still low, the input register accepts the next coming bits and forms a character. The character is then loaded to the buffer register. Subsequently, the parallel byte is transferred to the microprocessor when a request is made. Following signals are associated with the receiver section which are described below: RxD : It is Receive Data terminal. The serial bits are received on this line and converted to a parallel byte in the receiver input register. RxC : This pin is Receiver Clock. This controls the rate at which bits are received by the 8251A. In the asynchronous mode, the clock can be set to 1, 16 or 64 times of the baud. RxRDY : This is Receiver Ready pin. When this output terminal is high, the 8251A has a character in the buffer register and is ready to transfer it to the microprocessor. It can be used either to indicate the status or to interrupt the microprocessor. Fig. 14.14 14.6.4 Modem Control 437 The modem control section of the 8251A provides two input signals DSR (Data Set Ready) and (Clear to Send); and two output control signals (Data CTS DTR Terminal Ready) and RTS (Request to Send) to handle DTE and DCE. These signals are described as: DSR (Data Set Ready): This is an active low input terminal used by the modem to indicate that it is ready for communication. CTS (Clear to Send): This active low input terminal is used by the modem to signal the DTE that the communication channel is clear and it can send out the serial data. DTR (Data Terminal Ready): This output signal is used by the 8251 to signal the modem to indicate that the terminal is ready to communicate. RTS (Request to Send): This output signal is used by the 8251A to signal to modem that it has data to be transmitted. 14.7 INTERFACING OF 8251A Figure 14.15 shows the interfacing connection of 8251A with the microprocessor. The eight data lines of 8251A are to be connected to the data bus of the microprocessor. Fig. 14.15 438The RD and WR lines of 8251A are to be connected to the RD and WR of the control lines of 8085A microprocessor respectively. The CLK pin of the 8251A is be connected to the CLK out terminal of the microprocessor. The RESET pin is connected to the RESETOUT of the microprocessor. The terminal C / D is used to select the internal registers either control register or data register. So it is connected to the A address line of 0 the microprocessor. The chip select terminal CS of the PCI 8251A is to be connected to the output of an address decoder circuit. The address decoder circuit uses the address lines A to A of the microprocessor. From the decoder circuit used in this figure, the chip 1 7 select terminal of 8251A will be enabled when A and A are high and all other inputs are 7 4 low. The port addresses for reading the data word, writing the data word, reading the status word and writing the control word will be as shown in table 14.3. Table 14.3 A Function Port Address 0 RD WR 0 0 1 Read Data Word 90 H 0 1 0 Write Data Word 90 H 1 0 1 Read Status Word 91 H 1 1 0 Write Control Word 91 H 14.8 PROGRAMMING OF 8251A It has already been discussed that there is a 16 bit control register in a 8251A which contains two independent bytes (words). The first byte (word) is known as mode word which tells about the initialization parameters like mode (Asynchronous or Synchronous), baud, stop bits and parity bits etc. The second byte (word) is known as command word which tells about enabling the transmitter and receiver sections. The readiness of the peripherals can also be checked by reading the status word. 14.8.1 Initialization of 8251A in Asynchronous Mode To initialize 8251A in asynchronous mode, a certain sequence of control words must be followed. After a reset operation (through system RESET or through instruction) a mode word must be written into the control register followed by a command word. Any control word written into the control register immediately after the mode word will be interpreted as a command word that means a command word can be changed anytime during the operation. However, the 8251A should be reset prior to writing a new mode word, and it can be reset using internal reset bit (D ) in the command word. 6 Figure 14.16 shows the format of the mode word. The bits of this mode word are described below: Bits D -D : These bits program the baud rate factor. These bits are set 1 0 to 00 for synchronous operation. However, for asynchronous operation these bits specify the factor by which the transmit/receive clocks TxC and RxC , exceeds the baud rate. The other clock inputs CLK to the 8251A is used to generate the internal device timing and must simply be greater than 30 times the transmitter/receiver baud rate. 439 Fig. 14.16 Bits D -D : These bits specify the number of data bits in the character 3 2 is to be sent or received. Bit D : This bit enables the parity. If this bit is 0, the parity is 4 disabled. Bit D : This bit selects the even or odd parity. If this bit is 0, odd 5 parity is selected. The even parity is selected if this bit is 1. Bit D -D : These bits specify the number of stop bits. 6 7 Command Word Once the function definition of the 8251A has been programmed by the mode word instruction, the device is ready for data communication. The command word 440instruction controls the actual operation of the selected format. Functions such as Enable Transmit/ Receive, Error Reset and modem control are provided by the command word instruction. The format of the command word is shown in figure 14.17. Fig. 14.17 The bits of the command word are described below: Bit D : This bit enables the Transmitter. 0 Bit D : This bit controls the Data Terminal Ready. 1 Bit D : This bit enables the Receiver. 2 Bit D : This bit makes the transmitter to send continuous break 3 characters. 441Bit D : This resets the error flags. It resets Parity Error flag (PE), 4 Over Run Error flag (OE) and Framing Error flag (FE). Bit D : This bit controls the request to send to RTS pin of the 5 device. A high at this bit makes the RTS pin to become active. Bit D : It is used as an internal reset. A high to this bit resets the 6 device, so that a new mode word can be entered. Bit D : It is used in synchronous mode. It enables the receiver to 7 look for the synchronous data. Programming Sequence When programming the 8251A in asynchronous mode, following sequence must be followed: 1. Reset (either internal or external) 2. Mode Instruction (specify the asynchronous mode) 3. Command Instruction The resetting of the 8251A can be done by loading the control register with a command word whose D bit is high. This bit reset the device. The command word is, 6 therefore, loaded as: MVI A, 40 H ; Command word whose D bit is high is 6 loaded to accumulator. OUT 91 H ; Command word is loaded to control register whose port address is 91 H as discussed earlier. Now the mode instruction word is loaded to the control register. The mode word is formed as per the required modes of transmission. For example, for asynchronous transmission with 7 data bits, 2 stop bit and odd parity; also a 16 X clock is used. For this the format is shown in figure 14.18 and mode word will be given as: Fig. 14.18 MVI A, DA H ; Mode word is loaded to accumulator. OUT 91 H ; Mode word is loaded into control register. The command word with RTS, error reset and DTR enable with be given as shown in figure 14.19. 442

Advise: Why You Wasting Money in Costly SEO Tools, Use World's Best Free SEO Tool Ubersuggest.