what microprocessors are used in mobile phone. Lecture notes on advanced microprocessor and microcontroller and INTERFACING DEVICES pdf free download
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LECTURE NOTES ON MICROPROCESSORS AND INTERFACING DEVICES III B. Tech II semester (JNTUH-R13) Mr. S Lakshmanachari, Assistant Professor ELECTRICAL AND ELECTRONICS ENGINEERING INSTITUTE OF AERONAUTICAL ENGINEERING (AUTONOMOUS) DUNDIGAL, HYDERABAD - 500 043 Syllabus: JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD L T/ /P/D C III Year B.Tech. EEE -II Sem 4 -/-/- 4 MICROPROCESSORS AND INTERFACING DEVICES UNIT – I 8086 MICROPROCESSOR: Introduction to 8085 microprocessor, 8086 architecture- Functional Diagram, Register Organization, Memory segmentation, Memory addresses, physical memory organization, Signal descriptions of 8086- common function signals, Minimum and Maximum mode signals, Read Write cycles, Timing diagrams, Interrupt structure of 8086. UNIT – II ASSEMBLY LANGUAGE PROGRAMMING OF 8086: Instruction formats, addressing modes, instruction set, assembler directives, macros, Simple programs involving logical, branch and call instructions, Sorting, evaluating arithmetic expressions, string manipulations. UNIT – III PERIPHERAL INTERFACING WITH 8086 MICROPROCESSOR: 8255 PPI, Keyboard, display controllers, Stepper motor, A/D & D/A Converter Interfacing with 8086 microprocessor. Static and Dynamic memories, Vector interrupt table, Interrupt service routine, Introduction to DOS & BIOS interrupts, Programmable Interrupt Controller 8259, DMA controller 8257 Interfacing with 8086 microprocessor. UNIT – IV COMMUNICATION INTERFACE: Serial communication standards, serial data transfer schemes, 8251 USART architecture and Interfacing, RS-232, IEEE-488, prototyping and trouble shooting. UNIT – V INTRODUCTION TO MICROCONTROLLERS: Overview of 8051 microcontroller, Architecture, I/O ports and Memory organization, addressing modes and instruction set of 8051, Simple programs. UNIT-I 8086 ARCHITECTURE Introduction to processor:  A processor is the logic circuitry that responds to and processes the basic instructions that drives a computer.  The term processor has generally replaced the term central processing unit (CPU). The processor in a personal computer or embedded in small devices is often called a microprocessor.  The processor (CPU, for Central Processing Unit) is the computer's brain. It allows the processing of numeric data, meaning information entered in binary form, and the execution of instructions stored in memory. Evolution of Microprocessor: A microprocessor is used as the CPU in a microcomputer. There are now many different microprocessors available.  Microprocessor is a program-controlled device, which fetches the instructions from memory, decodes and executes the instructions. Most Micro Processor are single- chip devices.  Microprocessor is a backbone of computer system. which is called CPU  Microprocessor speed depends on the processing speed depends on DATA BUS WIDTH.  A common way of categorizing microprocessors is by the no. of bits that their ALU can Work with at a time  The address bus is unidirectional because the address information is always given by the Micro Processor to address a memory location of an input / output devices.  The data bus is Bi-directional because the same bus is used for transfer of data between Micro Processor and memory or input / output devices in both the direction.  It has limitations on the size of data. Most Microprocessor does not support floating-point operations.  Microprocessor contain ROM chip because it contain instructions to execute data.  What is the primary & secondary storage device? - In primary storage device the  Storage capacity is limited. It has a volatile memory. In secondary storage device the storage capacity is larger. It is a nonvolatile memory. a) Primary devices are: RAM (Read / Write memory, High Speed, Volatile Memory) / ROM (Read only memory, Low Speed, Non Voliate Memory) b) Secondary devices are: Floppy disc / Hard disk Compiler: Compiler is used to translate the high-level language program into machine code at a time. It doesn’t require special instruction to store in a memory, it stores automatically. The Execution time is less compared to Interpreter. 1.4-bit Microprocessor:  The first microprocessor (Intel 4004) was invented in 1971. It was a 4-bit calculation device with a speed of 108 kHz. Since then, microprocessor power has grown exponentially. So what exactly are these little pieces of silicone that run our computers(" Common Operating Machine Particularly Used For Trade Education And Research ")  It has 3200 PMOS transistors.  It is a 4-bit device used in calculator. 2.8-Bit microprocessor:  In 1972, Intel came out with the 8008 which is 8-bit.  In 1974, Intel announced the 8080 followed by 8085 is a 8-bit processor Because 8085 processor has 8 bit ALU (Arithmetic Logic Review). Similarly 8086 processor has 16 bit ALU. This had a larger instruction set then 8080. used NMOS transistors, so it operated much faster than the 8008. The 8080 is referred to as a “Second generation Microprocessor” 3. Limitations of 8 Bit microprocessor:  Low speed of execution  Low memory addressing capability  Limited number of general purpose registers  Less power full instruction set 4. Examples for 4/ 8 / 16 / 32 bit Microprocessors:  4-Bit processor – 4004/4040  8-bit Processor - 8085 / Z80 / 6800  16-bit Processor - 8086 / 68000 / Z8000  32-bit Processor - 80386 / 80486 5. What are 1st / 2nd / 3rd / 4th generation processor? st  The processor made of PMOS technology is called 1 generation processor, and it is made up of 4 bits nd  The processor made of NMOS technology is called 2 generation processor, and it is made up of 8 bits  The processor made of CMOS technology is called 3rd generation processor, and it is made up of 16 bits th  The processor made of HCMOS technology is called 4 generation processor, and it is made up of 32 bits (HCMOS : High-density n- type Complementary Metal Oxide Silicon field effect transistor) Block diagram of microprocessor: The Central Processing Unit (CPU): This device coordinates all operations of a micro computer. It fetches programs stored in ROM‟s or RAMs and executes the instructions depending one a specific Instructions set, which is characteristic of each type of CPU, and which is recognized by the CPU. The Random Access Memory (RAM): Temporary or trail programs are written. Besides the ROM area, every computer has some memory space for temporary storage of data as well as for programs under development. These memory devices are RAMs or Read – write memory. The contents of it are not permanent and are altered when power is turned off. So the RAM memory is considered to be volatile memory. The Read Only Memory (ROM): Permanent programs are stored. The permanent memory device/area is called ROM, because whatever be the memory contents of ROMs, they cannot be over written with some other information. For a blank ROM, the manufacturer supplies the device without any inf. In it, information can be entered electrically into the memory space. This is called burning a ROM or PROM. Data Lines/Data Bus: The number of data lines, like add. Lines vary with the specific CPU .The set of data lines is database like the address bus unlike add. Bus, the data bus is bidirectional because while the information on the address Bus always flows out of the CPU; the data can flow both out of the CPU as well as into the CPU. Control lines/ control Bus: The no. of control lines also depends on the specific CPU one is using. Ex: Read; Write lines are examples of control lines Clock: The clock is a symmetrical square wave signal that drives the CPU Instructions: An instruction is an elementary operation that the processor can accomplish. Instructions are stored in the main memory, waiting to be processed by the processor. An instruction has two fields:  Operation code, which represents the action that the processor must execute; Operand code, which defines the parameters of the action. The operand code depends on the operation. It can be data or a memory address Introduction to 8085 Microprocessor: The Salient Features of 8085 Microprocessor:  8085 is an 8 bit microprocessor, manufactured with N-MOS technology. 16  It has 16-bit address bus and hence can address up to 2 = 65536 bytes (64KB) memory locations through A -A . 0 15  The first 8 lines of address bus and 8 lines of data bus are multiplexed AD - AD . 0 7 Data bus is a group of 8 lines D - D . 0 7  It supports external interrupt request.8085 consists of 16 bit program counter (PC) and stack pointer (SP).  Six 8-bit general purpose register arranged in pairs: BC, DE, HL.  It requires a signal +5V power supply and can operate at 3 MHz, 5 MHz and 6 MHz Serial in/Serial out Port.  It is enclosed with 40 pins DIP (Dual in line package). Internal Architecture of 8085: 8085 Bus Structure: Address Bus:  The address bus is a group of 16 lines generally identified as A0 to A15.  The address bus is unidirectional: bits flow in one direction-from the MPU to peripheral devices.  The MPU uses the address bus to perform the first function: identifying a peripheral or a memory location. Data Bus:  The data bus is a group of eight lines used for data flow.  These lines are bi-directional - data flow in both directions between the MPU and memory and peripheral devices.  The MPU uses the data bus to perform the second function: transferring binary information.  The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF (28 = 256 numbers).  The largest number that can appear on the data bus is 11111111. Control Bus:  The control bus carries synchronization signals and providing timing signals.  The MPU generates specific control signals for every operation it performs. These signals are used to identify a device type with which the MPU wants to communicate. Registers of 8085:  The 8085 have six general-purpose registers to store 8-bit data during program execution.  These registers are identified as B, C, D, E, H, and L.  They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit operations. Accumulator (A):  The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).  This register is used to store 8-bit data and to perform arithmetic and logical operations.  The result of an operation is stored in the accumulator. Flags:  The ALU includes five flip-flops that are set or reset according to the result of an operation.  The microprocessor uses the flags for testing the data conditions.  They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The most commonly used flags are Sign, Zero, and Carry. The bit position for the flags in flag register is, 1. Sign Flag (S): After execution of any arithmetic and logical operation, if D7 of the result is 1, the sign flag is set. Otherwise it is reset. D7 is reserved for indicating the sign; the remaining is the magnitude of number. If D7 is 1, the number will be viewed as negative number. If D7 is 0, the number will be viewed as positive number. 2. Zero Flag (z): If the result of arithmetic and logical operation is zero, then zero flag is set otherwise it is reset. 3. Auxiliary Carry Flag (AC): If D3 generates any carry when doing any arithmetic and logical operation, this flag is set. Otherwise it is reset. 4. Parity Flag (P): If the result of arithmetic and logical operation contains even number of 1's then this flag will be set and if it is odd number of 1's it will be reset. 5. Carry Flag (CY): If any arithmetic and logical operation result any carry then carry flag is set otherwise it is reset. Arithmetic and Logic Unit (ALU):  It is used to perform the arithmetic operations like addition, subtraction, multiplication, division, increment and decrement and logical operations like AND, OR and EX-OR.  It receives the data from accumulator and registers.  According to the result it set or reset the flags. Program Counter (PC):  This 16-bit register sequencing the execution of instructions.  It is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register.  The function of the program counter is to point to the memory address of the next instruction to be executed.  When an opcode is being fetched, the program counter is incremented by one to point to the next memory location. Stack Pointer (SP):  The stack pointer is also a 16-bit register used as a memory pointer.  It points to a memory location in R/W memory, called the stack.  The beginning of the stack is defined by loading a 16-bit address in the stack pointer (register). Temporary Register: It is used to hold the data during the arithmetic and logical operations. Instruction Register: When an instruction is fetched from the memory, it is loaded in the instruction register. Instruction Decoder: It gets the instruction from the instruction register and decodes the instruction. It identifies the instruction to be performed. Serial I/O Control: It has two control signals named SID and SOD for serial data transmission. Timing and Control unit:  It has three control signals ALE, RD (Active low) and WR (Active low) and three status signals IO/M(Active low), S0 and S1.  ALE is used for provide control signal to synchronize the components of microprocessor and timing for instruction to perform the operation.  RD (Active low) and WR (Active low) are used to indicate whether the operation is reading the data from memory or writing the data into memory respectively.  IO/M(Active low) is used to indicate whether the operation is belongs to the memory or peripherals.  If, Interrupt Control Unit:  It receives hardware interrupt signals and sends an acknowledgement for receiving the interrupt signal. Pin Diagram and Pin Description Of 8085 8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as follows 1. Power supply and clock signals 2. Address bus 3. Data bus 4. Control and status signals 5. Interrupts and externally initiated signals 6. Serial I/O ports 1. Power supply and clock frequency signals  Vcc + 5 volt power supply  Vss Ground  X1, X2: Crystal or R/C network or LC network connections to set the frequency of internal clock generator.  The frequency is internally divided by two. Since the basic operating timing frequency is 3 MHz, a 6 MHz crystal is connected externally.  CLK (output)-Clock Output is used as the system clock for peripheral and devices interfaced with the microprocessor. 2. Address Bus:  A8 - A15 (output; 3-state)  It carries the most significant 8 bits of the memory address or the 8 bits of the I/O address; 3. Multiplexed Address / Data Bus:  AD0 - AD7 (input/output; 3-state)  These multiplexed set of lines used to carry the lower order 8 bit address as well as data bus.  During the opcode fetch operation, in the first clock cycle, the lines deliver the lower order address A0 - A7.  In the subsequent IO / memory, read / write clock cycle the lines are used as data bus.  The CPU may read or write out data through these lines. 4. Control and Status signals:  ALE (output) - Address Latch Enable.  This signal helps to capture the lower order address presented on the multiplexed address / data bus.  RD (output 3-state, active low) - Read memory or IO device.  This indicates that the selected memory location or I/O device is to be read and that the data bus is ready for accepting data from the memory or I/O device.  WR (output 3-state, active low) - Write memory or IO device.  This indicates that the data on the data bus is to be written into the selected memory location or I/O device.  IO/M (output) - Select memory or an IO device.  This status signal indicates that the read / write operation relates to whether the memory or I/O device.  It goes high to indicate an I/O operation.  It goes low for memory operations. 5. Status Signals:  It is used to know the type of current operation of the microprocessor. 6. Interrupts and externally initiated operations:  They are the signals initiated by an external device to request the microprocessor to do a particular task or work.  There are five hardware interrupts called,  On receipt of an interrupt, the microprocessor acknowledges the interrupt by the active low INTA (Interrupt Acknowledge) signal. Reset In (input, active low)  This signal is used to reset the microprocessor.  The program counter inside the microprocessor is set to zero.  The buses are tri-stated. Reset Out (Output)  It indicates CPU is being reset.  Used to reset all the connected devices when the microprocessor is reset 7. Direct Memory Access (DMA): Tri state devices:  3 output states are high & low states and additionally a high impedance state.  When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is 0, Q is 1, otherwise Q is 0). However, when E is low the gate is disabled and the output Q enters into a high impedance state.  For both high and low states, the output Q draws a current from the input of the OR gate.  When E is low, Q enters a high impedance state; high impedance means it is electrically isolated from the OR gate's input, though it is physically connected. Therefore, it does not draw any current from the OR gate's input.  When 2 or more devices are connected to a common bus, to prevent the devices from interfering with each other, the tristate gates are used to disconnect all devices except the one that is communicating at a given instant.  The CPU controls the data transfer operation between memory and I/O device. Direct Memory Access operation is used for large volume data transfer between memory and an I/O device directly.  The CPU is disabled by tri-stating its buses and the transfer is effected directly by external control circuits.  HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the microprocessor acknowledges the request by sending out HLDA signal and leaves out the control of the buses. After the HLDA signal the DMA controller starts the direct transfer of data. READY (input)  Memory and I/O devices will have slower response compared to microprocessors.  Before completing the present job such a slow peripheral may not be able to handle further data or control signal from CPU.  The processor sets the READY signal after completing the present job to access the data.  The microprocessor enters into WAIT state while the READY pin is disabled. 8. Single Bit Serial I/O ports:  SID (input) - Serial input data line  SOD (output) - Serial output data line  These signals are used for serial communication. Overview or Features of 8086  It is a 16-bit Microprocessor (μp).It’s ALU, internal registers works with 16bit binary word. 20  8086 has a 20 bit address bus can access up to 2 = 1 MB memory locations.  8086 has a 16bit data bus. It can read or write data to a memory/port either 16bits or 8 bit at a time.  It can support up to 64K I/O ports.  It provides 14, 16 -bit registers.  Frequency range of 8086 is 6-10 MHz  It has multiplexed address and data bus AD0- AD15 and A16 – A19.  It requires single phase clock with 33% duty cycle to provide internal timing.  It can prefetch upto 6 instruction bytes from memory and queues them in order to speed up instruction execution.  It requires +5V power supply.  A 40 pin dual in line package.  8086 is designed to operate in two modes, Minimum mode and Maximum mode. o The minimum mode is selected by applying logic 1 to the MN / MX input pin. This is a single microprocessor configuration. o The maximum mode is selected by applying logic 0 to the MN / MX input pin. This is a multi micro processors configuration. Register Organization of 8086 General purpose registers The 8086 microprocessor has a total of fourteen registers that are accessible to the programmer. It is divided into four groups. They are:  Four General purpose registers  Four Index/Pointer registers  Four Segment registers  Two Other registers General purpose registers: Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the low order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations and string manipulation. Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing. Count register consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low order byte of the word, and CH contains the high-order byte. Count register can be used in Loop, shift/rotate instructions and as a counter in string manipulation Data register consists of two 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low order byte of the word, and DH contains the high-order byte. Data register can be used as a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number. Index or Pointer Registers These registers can also be called as Special Purpose registers. Stack Pointer (SP) is a 16-bit register pointing to program stack, i.e. it is used to hold the address of the top of stack. The stack is maintained as a LIFO with its bottom at the start of the stack segment (specified by the SS segment register).Unlike the SP register, the BP can be used to specify the offset of other program segments. Base Pointer (BP) is a 16-bit register pointing to data in stack segment. It is usually used by subroutines to locate variables that were passed on the stack by a calling program. BP register is usually used for based, based indexed or register indirect addressing. Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions. Used in conjunction with the DS register to point to data locations in the data segment. Destination Index (DI) is a 16-bit register. Used in conjunction with the ES register in string operations. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions. In short, Destination Index and SI Source Index registers are used to hold address. Segment Registers Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers. Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions. Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction. Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions. Extra segment (ES) used to hold the starting address of Extra segment. Extra segment is provided for programs that need to access a second data segment. Segment registers cannot be used in arithmetic operations. Other registers of 8086 Instruction Pointer (IP) is a 16-bit register. This is a crucially important register which is used to control which instruction the CPU executes. The IP, or program counter, is used to store the memory location of the next instruction to be executed. The CPU checks the program counter to ascertain which instruction to carry out next. It then updates the program counter to point to the next instruction. Thus the program counter will always point to the next instruction to be executed. Flag Register contains a group of status bits called flags that indicate the status of the CPU or the result of arithmetic operations. There are two types of flags: 1. The status flags which reflect the result of executing an instruction. The programmer cannot set/reset these flags directly. 2. The control flags enable or disable certain CPU operations. The programmer can set/reset these bits to control the CPU's operation. Nine individual bits of the status register are used as control flags (3 of them) and status flags (6 of them).The remaining 7 are not used. A flag can only take on the values 0 and 1. We say a flag is set if it has the value 1.The status flags are used to record specific characteristics of arithmetic and of logical instructions. Control Flags: There are three control flags 1. The Direction Flag (D): Affects the direction of moving data blocks by such instructions as MOVS, CMPS and SCAS. The flag values are 0 = up and 1 = down and can be set/reset by the STD (set D) and CLD (clear D) instructions. 2. The Interrupt Flag (I): Dictates whether or not system interrupts can occur. Interrupts are actions initiated by hardware block such as input devices that will interrupt the normal execution of programs. The flag values are 0 = disable interrupts or 1 = enable interrupts and can be manipulated by the CLI (clear I) and STI (set I) instructions. 3. The Trap Flag (T): Determines whether or not the CPU is halted after the execution of each instruction. When this flag is set (i.e. = 1), the programmer can single step through his program to debug any errors. When this flag = 0 this feature is off. This flag can be set by the INT 3 instruction. Status Flags: There are six status flags 1. The Carry Flag (C): This flag is set when the result of an unsigned arithmetic operation is too large to fit in the destination register. This happens when there is an end carry in an addition operation or there an end borrows in a subtraction operation. A value of 1 = carry and 0 = no carry. 2. The Overflow Flag (O): This flag is set when the result of a signed arithmetic operation is too large to fit in the destination register (i.e. when an overflow occurs). Overflow can occur when adding two numbers with the same sign (i.e. both positive or both negative). A value of 1 = overflow and 0 = no overflow. 3. The Sign Flag (S): This flag is set when the result of an arithmetic or logic operation is negative. This flag is a copy of the MSB of the result (i.e. the sign bit). A value of 1 means negative and 0 = positive. 4. The Zero Flag (Z): This flag is set when the result of an arithmetic or logic operation is equal to zero. A value of 1 means the result is zero and a value of 0 means the result is not zero. 5. The Auxiliary Carry Flag (A): This flag is set when an operation causes a carry from bit 3 to bit 4 (or a borrow from bit 4 to bit 3) of an operand. A value of 1 = carry and 0 = no carry. 6. The Parity Flag (P): This flags reflects the number of 1s in the result of an operation. If the number of 1s is even its value = 1 and if the number of 1s is odd then its value = 0. Architecture of 8086 or Functional Block diagram of 8086  8086 has two blocks Bus Interface Unit (BIU) and Execution Unit (EU).  The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue.  EU executes instructions from the instruction system byte queue.  Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance.  BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.  EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register. Figure: 8086 Architecture Explanation of Architecture of 8086 Bus Interface Unit:  It provides a full 16 bit bidirectional data bus and 20 bit address bus.  The bus interface unit is responsible for performing all external bus operations.  Specifically it has the following functions:  Instruction fetch Instruction queuing, Operand fetch and storage, Address relocation and Bus control.  The BIU uses a mechanism known as an instruction stream queue to implement pipeline architecture.  This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction.  These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle.  After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output.  The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory.  These intervals of no bus activity, which may occur between bus cycles are known as Idle state.  If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle.  The BIU also contains a dedicated adder which is used to generate the 20bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address.  For example: The physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register.  The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write. Execution Unit  The Execution unit is responsible for decoding and executing all instructions.  The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write bus cycles to memory or I/O and perform the operation specified by the instruction on the operands.  During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction.  If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue.  When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions.  Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue.

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