How 8085 Microprocessor

8085 Microprocessor
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Published Date:25-10-2017
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5 The 8085 Microprocessor After the study of conceptual computers SAP-I, SAP-II and SAP-III, we are now in the position to understand the fundamentals of 8-bit microprocessor 8085. As discussed in the preceding chapters, the basic components of all the computers are Keyboard, Display devices, Memory devices and Central Processing unit. The central processing unit (CPU) is the heart of the computer and also called microprocessor. The technological revolution brought in recent years, the invention of micro- programmable computer on microprocessor chip. First four bit microprocessor chip INTEL-4004 was developed by Intel Corporation of America in 1971. Intel introduced in 1972 an 8-bit microprocessor 8008 and in 1973 another 8-bit microprocessor 8080. The microprocessor 8080 was the most popular microprocessor of the early 70s. In the year 1974, Intel developed a 40 pin microprocessor chip 8085, which was the enhanced version of 8080. Intel 8080 microprocessor was not in fact a complete CPU on a chip because the clock and controller were on separate chip. Further, it utilizes two separate power supplies. The 8085 microprocessor has the advantages over 8080 that it has on- chip clock and control circuit. It needs only one power supply of +5 volts. 5.1 ARCHITECTURE OF 8085 MICROPROCESSOR Intel 8085, an 8-bit NMOS microprocessor is available in the form of 40 Pin dual in line IC package. It is fabricated on a single LSI chip. It operates on +5 V d.c. supply. The clock speed used in this microprocessor is about 3 MHZ. General Purpose 8-bit 16 microprocessor is capable of addressing up to 64 K bytes (i.e. 2 = 65536 bytes) of memory. The functional block diagram is shown in figure 5.1. The main functional components of 8085A microprocessor are as given below: (i) Register Section (ii) Arithmetic and Logic Unit (iii) Timing and Control Section (iv) Interrupt Control (v) Serial Input / Output Control Fig. 5.1 1265.1.1 Register Section The 8085 microprocessor contains eight addressable 8-bit registers namely: A (Accumulator) register F Flag register (Flag flip-flops) B register C register D register E register H register L register Out of these registers B, C, D, E, H and L registers are 8-bit general purpose registers. These registers can either be used as single register or a combination of two registers as 16 bit register pair. As discussed in SAP-III computers, the valid register pairs are B-C, D-E or H-L register pairs. The higher order byte of 16 bit data is stored in first register (B in B-C register pair), and low order byte in the second register (C in B-C register pair). The H-L register pair can also be used for register indirect addressing; since this register pair can also function as data pointer. The large number of general purpose registers gives more flexibility and ease in the programming. However, the general purpose registers are limited as registers occupy more space on the silicon chip. Beside these general purpose registers, the 8085 has remaining two 8-bit registers Accumulator (A) and Flag (F) as special purpose registers and two 16 bit registers namely Program counter (PC) and stack pointer (SP). Accumulator (A) As discussed in preceding chapters, accumulator is a 8 bit buffer register extensively used in arithmetic, logic, load and store operations as well as in input / output instructions. All the arithmetic and logical operations are performed on the accumulator contents; i.e. one of the operand is always taken into the accumulator. Flag (F) Register It is an 8-bit register associated with the execution of instructions in the microprocessor. Out of the 8 bits of flag register, 5 bits contains significant information in terms of status flags. The five flags are: (i) Sign flag (S) (ii) Zero flag (Z) (iii) Carry flag (CY) (iv) Parity flag (P) (v) Auxiliary Carry flag (AC) All the flags except the Auxiliary carry (AC) flag have been discussed in SAP-III computers. 127The bit positions reserved for these flags in the flag register (F) is shown in figure 5.2. Fig. 5.2 (i) Sign flag (S) The sign flag is set (S = 1), if the result of the operation of the instruction is negative (MSB of the result is 1); otherwise it is reset (S = 0) for the positive result (MSB is zero). (ii) Zero flag (Z) The zero flag is set (Z = 1) if the result of the operation of the instruction is zero otherwise this flag is reset (Z = 0). i.e. Z = 1 if the result is zero, and Z = 0 if the result is not zero. (iii) Carry flag (CY) The carry flag is set to 1, if there exist a carry (or borrow) to th the highest order bit (non-existent 9 position) as a result of the execution of addition or subtraction instructions. If there is no carry (or borrow) to the higher order bit, the carry flag is reset. i.e. CY = 1 if there is a carry to the highest order bit (or overflow), and CY = 0 if there is no carry to the highest order bit (or no overflow). 128(iv) Parity flag (P) After an arithmetic and logic operation, if the result has even number of 1s, then parity bit is set. If on the other hand the result has odd number of 1s, the parity flag is reset. i.e. P = 1, if the result has even number of 1s, and P = 0, if the result has odd number of 1s. (v) Auxiliary carry (AC) This is a new flag in 8085 microprocessor. This flag (AC) is set to 1, if there is an overflow at bit 3 of the accumulator. AC flag is used in BCD arithmetic. This is illustrated as given below: As shown in figure 5.2, the five bits in flag register are defined. The three bits are undefined. The Accumulator and 8 bits (including three undefined bits) of flag register form a Program Status Word (PSW). The accumulator and flag registers are treated as a 16 bit unit for stack operation. Program Counter – 16 bit register The program counter is a 16 bit register. It is used to send 16 bit address to fetch the instruction from the memory. It acts as a pointer which indicates the address of the next instruction to be fetched and executed. The program counter is updated after an instruction has been fetched by the processor. If an instruction is one byte instruction, then the program counter will be updated by one (i.e. PC = PC + 1). Similarly, for two and three byte instructions, the program counter will be updated by two (i.e. PC = PC + 2) or three (i.e. PC = PC + 3) locations respectively. Stack Pointer – 16 bit register The stack is an area of RAM (random access memory or read / write memory) in which temporary information is stored. It is stored on First-In-Last-Out (FILO) basis. An address in the RAM area is assigned to the stack pointer where the first information is stored as the first stack entry. This is done by initializing stack pointer by an instruction. Higher stack entries are made at the progressively decreasing addresses. 5.1.2 Address Buffer and Address-Data Buffer It has already been discussed that 8085 requires 8-bit data bus and 16-bit address bus, as the memory address is of 16 bits. More number of IC pins are required if separate address and data bus are introduced. To restrict the number of pins of 8085 to only 40, lower address lines A -A and data lines D -D are used in multiplexed mode. The 0 7 0 7 multiplexed lines are designed as Address/Data Bus (AD -AD ). So whenever 16-bit 0 7 address is transmitted by the microprocessor 8 MSBs of the address lines are sent on the Address Bus (A -A ) and 8 LSBs of the lines are sent on the Address/Data Bus (AD - 15 8 7 AD ). The 8 LSBs of the address are then latched either into memory or external latch so 0 that the complete address remains available for further operation. The 8-bit Address/Data Bus will now be free for the data transmission. 5.1.3 Arithmetic and Logical Unit (ALU) 129 The arithmetic and logical unit (ALU) basically consists of accumulator (A), flag register (F) and a temporary register (which is inaccessible by the programmer or user). This unit carries out the arithmetic and logic calculations of the data stored in general purpose registers or in memory locations. The arithmetic operations are ADD, SUB, compare, increments, decrements and complements etc.; while logical operations are AND, OR, XOR and Rotate. The result of these operations could be placed in the accumulator or elsewhere through the internal bus. Arithmetic operations are usually carried out in 2’s complement adder / subtrator discussed in the preceding chapter. For these operations, ALU receives the control signals from the timing and control unit. 5.1.4 Timing and Control Unit This unit consists of the following sections: 1. Instruction Register and Decoder 2. Control signals 1. Instruction Register and Decoder As discussed in the preceding chapter, the CPU fetches an instruction from the memory for its execution. This instruction can be of 1-3 byte long. The first byte contains the op code of instruction which basically specifies the nature of operation to be performed indicating the length of the instruction. The first byte (op code of the instruction) transferred to 8-bit instruction register through the internal bus of the CPU, becomes available at the instruction decoder. The decoder decodes the op code and directs the control unit to produce the necessary control signals. 2. Control Signals Following are the control signals of 8085 microprocessor needed for the operation of CPU. (i) X , X and CLK Out 1 2 Two pins X and X are provided to be externally connected to a quartz crystal. 1 2 The clock signal of fixed frequency is generated through the internal circuitry of the processor. The frequency at which the microprocessor 8085 works is half of the crystal frequency. The quartz crystal of 6.144 MHz is used in this processor. This gives the clock frequency of 3.072 MHz (half of the crystal frequency) of 50% duty cycle. The clock period is of about 320 nsec. The output of the clock frequency is also available at CLK out terminal. (ii) Address Latch Enable (ALE) The 16 bit address bus is basically divided into two sets. The most significant bits A -A of the address bus are used separately and the least significant bits of the address 7 15 AD -AD are time multiplexed with the bits of bidirectional data bus (D -D ). The AD - 0 7 0 7 0 AD bus serves the dual purpose as they can be used as low-order address bus as well as 7 bidirectional data bus at different times. This is used as address bus, during the first clock cycle of the machine cycle involving memory; and during the remaining clock cycle of the machine cycle, it acts as the data bus. This is accomplished by address latch enable (ALE) signal provided in the processor. During the first clock cycle of the machine cycle ALE is high which enables the lower 8-bit of the address to be latched either into the memory or external latch. (iii) R (Read ) Signal D 130 This is an active low signal to be connected to memory read input (output enable signal to memories) or to input / output read signal to enable input / output buffer. (iv) W (Write) Signal R Similar to read signal ( R ), write signal (W ) is also active low. This signal is D R used to write to the memory or input / output devices. (v) IO/ M (Input Output / Memory) This signal IO/ M distinguishes that the address and data is meant for either I/O devices or memory. Whenever this signal is high (1), microprocessor will communicate to the I/O devices and whenever it is low (0), microprocessor will communicate to the memory. (vi) Status Signals (S , S ) 0 1 The status signals (S , S ) along with IO/ M signal indicate the type of machine 0 1 cycle in progress. The type of machine cycle are op code fetch cycle, memory read cycle, memory write cycle, I/O read cycle or I/O write cycle. Various types of status codes are given in table 5.2. Table 5.2 Machine Cycle S S 1 0 IO/M Op code fetch Cycle 0 1 1 Memory Read Cycle 0 1 0 Memory Write Cycle 0 0 1 I/O Read Cycle 1 1 0 I/O Write Cycle 1 0 1 INTR Acknowledge 1 1 1 Halt Hi-Z 0 0 (vi) Hold and HLDA HOLD and HLDA (Hold Acknowledge) signals are used for DMA (Direct Memory Access) operation. In a microprocessor, the data transfer between I/O devices and memory will take place through the microprocessor. The involvement of the processor slows down the data transfer between I/O devices and memory. The transfer of data directly from I/O devices to memory without involvement of microprocessor is called DMA. The DMA will save the time as CPU relinquishes the control of Buses. In this way DMA transfers the large amount of data in a relatively short time. The HOLD and HLDA signals are used in the operation. Whenever HOLD signal is high, CPU temporarily relinquishes its operation by floating the address, data and control buses; and DMA operation is started. A high HLDA (Hold Acknowledge) signal is also sent to DMA controller, indicating that CPU has received the hold request. Whenever the data transfer is complete, then the control to CPU is returned back by sending a HOLD signal. Further the HLDA signal goes low. (viii) READY signal (Input) Some peripheral devices connected to 8085 microprocessor operate at much slower speed than the processor. To synchronize the speed of CPU and peripheral devices or to slow down the speed of 8085, the READY signal is used. If the READY signal is high the peripheral device is ready and the processor can complete the data transfer. If 131this signal is low the microprocessor waits (by generating a number of NOP T-states) till it goes high. (ix) and RESET OUT The signal may be low from the operator Reset button or from the processor. When the signal is low, the CPU will reset the program counter, instruction register and other circuits. It also sends a high RESET OUT. The RESET OUT signal goes to peripheral devices to reset or initialized. When signal goes high and RESET OUT goes low, the data processing may begin. 5.1.5 Interrupt Control Sometimes it is necessary to interrupt the execution of the main program. For this an interrupt request is obtained from the I/O devices. After receiving the interrupt request (INTR), processor temporarily stops what it was doing and attends to the I/O device. INTA is an interrupt acknowledge signal which is sent by the microprocessor after INTR signal is received. After the work of the I/O device is complete it returns to what it was doing earlier. Basically 8085A has five hardware interrupts namely: INTR RST 5.5 RST 6.5 RST 7.5 and TRAP If two or more of these interrupts are active at the same time, the 8085 takes them in order of priority level. The priority levels of these interrupts are given in table 5.3. Table 5.3 Interrupts Priority TRAP 1 RST 7.5 2 RST 6.5 3 RST 5.5 4 INTR 5 The details of these instructions will be discussed in chapter 7. 5.1.6 Serial I/O Control Serial input / output control circuit incorporated in this microprocessor is used for the data transmission. For this purpose two pins SID and SOD are provided in the serial input/output control unit. The SID (Serial Input Data) terminal receives the serial data stream from an input device, the control unit converts serial data stream to parallel data before it is used by the computer. After the conversion 8-bit parallel data is stored in the accumulator. Similarly, SOD (Serial Out Data) terminal outputs the 8-bit parallel available with the accumulator into serial form to the peripheral device connected with the computer. 5.2 PIN DESCRIPTION OF 8085 132 The pin details and logical schematics of the 40 pin dual line package (DIP) IC 8085 are shown in figures 5.3(a) and (b) respectively. Fig. 5.3 (c) shows the shape of the microprocessor. The descriptions of various pins of the microprocessor are given below: Fig. 5.3 (a) 133 Fig. 5.3 (b) Fig. 5.3 (c) 134PIN NOS. 1 and 2: These X and X pins are to be connected to an external quartz crystal, L-C or R-C 1 2 network which drives the internal clock generator. The clock signal of appropriate frequency is determined when a quartz crystal is connected to the on-chip oscillator as shown in figure 5.4(a). The oscillator output from the Schmitt trigger drives a flip-flop which divides the frequency by a factor of two. The circuit produces two clock signals Φ1 (CLK) and Φ2 ( CLK ) to derive the internal circuit of the microprocessor. A 6.25 MHz crystal is used to provide 3.125 MHz internal clock frequency. Generally, quartz crystal is used for the On-chip oscillator for the accurate and stable clock frequency, though a parallel resonant L-C circuit may be used for the frequency determining network as shown in figure 5.4(b). The network produces a signal whose frequency tolerance is about ±10% . The component values may be chosen from the following formula: 1 f = 2π L(C + C ) in The input capacitance Cin is approximately 15 Pf. To minimize the variations in frequency, it is recommended to choose C as 30 Pf. Fig. 5.4(a) 135 Fig. 5.4 (b) Fig. 5.4 (c) An R-C network may also be used as the frequency determining network for the on-chip oscillator of the microprocessor as shown in figure 5.4(c). The driving frequency generated by this circuit is approximately 3MHz. It is not recommended to use the frequencies higher or lower than this. PIN NO. 3 This is RESET OUT signal, which indicates that CPU is being reset. When it is high, system is reset. The signal is synchronized to the processor clock and lasts for an integral number for clock periods. When the RESET OUT signal goes low, the processing begins. PIN NOS. 4 and 5 Pin Nos. 4 and 5 indicate SOD (Serial Out Data) and SID (Serial In Data) terminals respectively. These pins are associated with Serial Input/Output control unit for 8085 microprocessor. As already discussed these pins are used for the serial data transmission. The SOD output pin can deliver a serial data stream to a peripheral device. On executing SIM (Set Interrupt Mask) instruction, if bit D is set to 1, the content of D 6 7 bit (set or reset) of the accumulator is latched on the SOD pin as shown in figure 5.5(a). 136 Fig. 5.5 (a) The data on the SID line (PIN 5) loads into accumulator at bit D whenever a RIM 7 instruction is executed as shown in figure 5.5(b). The details of SIM and RIM instructions will be discussed in chapter 7. Fig. 5.5 (b) PIN NOS. 6 to 11 137 The interrupt control unit of the microprocessor contains these pins. The Pins 6 to 11 are restart interrupts named as: TRAP (Pin No.6) I Priority RST 7.5 (Pin No. 7) II Priority RST 6.5 (Pin No. 8) III Priority RST 5.5 (Pin No. 9) IV Priority INTR (Pin No. 10) V Priority The TRAP has the highest priority and INTR has the lowest priority. The priority level is of importance if two or more interrupts become active at the same time. The TRAP is non-maskable interrupt. It is both edge and level sensitive. The interrupts (TRAP, RST 7.5, RST 6.5 and RST 5.5) are also called vector interrupts, as each interrupt has fixed memory location (vector location) for the transfer of control from the normal execution of the routine. The vector locations of these interrupts are given in table 5.4. As soon as any of these pins 6 to 10 are active (high), the internal circuit of 8085 stops the normal execution of program and the program control is transferred to the corresponding memory location (vector location). Table 5.4 Interrupts Memory locations TRAP 0024 H RST 7.5 003C H RST 6.5 0034 H RST 5.5 002C H INTR (Pin No. 10) is a general purpose interrupt and has the lowest priority. As soon as Pin No. 10 is high, the microprocessor stops the execution of normal program and after completing the instruction at hand, it goes to CALL instruction. The INTR is enabled or disabled by the instructions ET (Enable Interrupts) or DI (Disable Interrupts) respectively. The Pin No. 11 is an Interrupt Acknowledge ( INTA ) signal. A low (logic 0) to this pin indicate that the microprocessor has acknowledged the request from the peripheral device. It is also used to activate the interrupt controller. PIN NOS. 12 to 19 Pin Nos. 12 to 19 (AD -AD ) form bi-directional multiplexed Address/Data Bus. 0 7 The least significant 8 bits of the memory address (or I/O Address) appear on the bus during the first T-states of a machine cycle. It then becomes the data bus during the next T-states. PIN NO. 20 Pin No. 20 is the ground terminal. PIN NOS. 21 to 28 The Pin Nos. 21 to 28 (A8-A15) form unidirectional most significant 8 bits of memory address or 8 bits of the I/O address. It remains in the high impedance state during HOLD, HALT and RESET modes. PIN NOS. 29 to 33 138 The Pin Nos. 29 to 33 labled as S and S respectively are known as status signals. 0 1 These status signals along with signal indicate the various operations as indicated IO/ M in table 5.5. Table 5.5 Machine cycle Status Control signals IO/M S S 1 0 Op code Fetch 0 1 1 RD = 0 Memory Read 0 1 0 RD = 0 Memory Write 0 0 1 WR = 0 I/O Read 1 1 0 RD = 0 I/O Write 1 0 1 WR = 0 Interrupt Ack. 1 1 1 INTA = 0 HALT HI-Z 0 0 HOLD HI-Z X X RD , WR = Z RESET HI-Z X X INTA = 1 HI-Z = High Impedance State X = Unspecified PIN NO. 30 The Pin No. 30 is known as ALE (Address Latch Enable) terminal. When this signal is high the information carried on the multiplexed address/data bus (AD -AD ) is 0 7 the lower 8 bits of the address. It also enables the low order address (AD -AD ) from the 0 7 multiplexed address/data bus to latch either into the memory or the external latch. The ALE signal separates the low order address and data from the multiplexed Address/data Bus. This is illustrated in figure 5.6. 139 Fig. 5.6 PIN NOS. 31, 32 and 34 The Pin Nos. 31 and 32 are the two control signals WR (Write bar) and RD (Read bar) respectively. The pin 34 carries IO/ M signal which is one of the status signals. The other status signals are S0 and S1 discussed earlier. A low WR signal generated by the microprocessor sends (writes) data into I/O devices or memory. Similarly, a low RD signal generated by the microprocessor reads (receives) the data from the I/O devices or memory locations. The IO/ M signal indicates whether the address on the address bus is meant for I/O devices. However, a low to this signal indicates that the address on the address bus is meant for memory location. The RD , WR and IO/ M signals function together. PIN NO. 35 140 The Pin No. 35 is known as READ signal which forces the microprocessor to wait till the data become available from the memory or input/output devices. This signal is needed to synchronize the speed of the microprocessor with I/O devices or memory as the memory or I/O devices are not as fast as the microprocessor. When the READ signal is low, the microprocessor waits till the READY signal is 1. As soon as READY signal is 1, the microprocessor knows that the data are available from the memory or I/O devices. PIN NO. 36 This pin is signal. This input carrying signal may be operated by the operator using the RESET button provided externally or it may be operated directly from the other source. When this signal is low (momentarily), the CPU will reset the program counter, instruction register, all interrupts (except TRAP) are disabled, SOD signal becomes low and Data, address and control buses are floated. When this signal goes high, the data processing begins. PIN NO. 37 This pin carries CLK OUT signal. It is derived from the on-chip oscillator, which goes to peripherals to synchronize their timings. PIN NOS. 38-39 The Pin Nos. 38 and 39 are the HOLD and HLDA (Hold Acknowledge) signals respectively. These signals are used in DMA (Direct Memory Access) operations. As shown in figure 5.7, when any I/O device indicates that the data are ready for DMA transfer, a high HOLD signal is sent by the DMA controller to the 8085 microprocessor. It is in fact a request signal from the DMA controller to the microprocessor. The microprocessor then sends a high signal to DMA controller indicating that the microprocessor has received the request from the I/O devices and will relinquish the address, data and control bus after completing the current instruction. The DMA controller thus carries out the data transfer. A low HOLD signal will return the control to the microprocessor. 141 Fig. 5.7 PIN NO. 40 The pin 40 is +VCC, which is to be externally connected to +5 volt d.c. supply. 5.3 INSTRUCTION SET OF 8085 MICROPROCESSOR The 8085 includes all the instructions of SAP-III. In addition there are few more instructions which will be discussed below. These new instructions were not considered in SAP-3 because of its architecture. LHLD address (Loads the H-L pair direct) This instruction loads the H-L pair direct with two bytes already stored in two consecutive memory locations starting at the specified memory address. The contents stored in the memory location whose address is given with the instruction will be loaded to the L-register; and the contents stored in the next memory location (address + 1) will be loaded to the H-register. L← M i.e. address and H← M address+1 For example, let 2A H is stored in the memory location 2100 H and 2B H is stored in the memory location 2101 H, then after the execution of the instruction LHLD 2100 H , the L-register will have 2A H and H-register will have 2B H. None of the flags is affected with this instruction. SHLD address (Stores the H-L pair direct) This instruction does the reverse operation of LHLD. The instruction SHLD address stores the contents of L-register to memory location whose address is given with the instruction; and the contents of H-register are stored in the next consecutive memory location (address + 1). 142i.e. M ← L address M ← H and address+1 No flag is affected with this instruction too. L = H = For example, if 3A H and 3B H, then after the execution of the instruction SHLD 2200 H will result. M ← 3A 2200H and M ← 3B 2201H LDAX rp (Loads the Accumulator Indirect) This instruction loads the accumulator, the contents already stored in the memory location addressed by the register pair (rp). Here rp represents B-C or D-E register pair. The H-L register pair is not included in this instruction. i.e. A← M rp The possible combinations of the instruction are: LDAX B LDAX D No flag is affected with the execution of this instruction. For example, if D = 25 H, E = 00 H and M = 34 H, 2500 H then after the execution of the instruction LDAX D, the accumulator will have: A← M 2500H i.e. A = 34 H It is worth while to mention that the instruction LDAX H does not exist, because the contents stored in the memory location addressed by H-L register pair may be loaded to accumulator by the instruction MOV A, M. STAX rp (Stores the Accumulator Indirect) The STAX rp instruction does the reverse operation of LDAX rp. This instruction stores the accumulator contents in the memory location addressed by the register pair (rp). Here too rp represents B-C or D-E register pair. The H-L register pair is not included in this instruction. i.e. M ← A rp The possible combination of this instruction are: STAX B STAX D No flag is affected with the execution of this instruction. For example, if B = 21 H, C = 00 H and A = 3A H, then after the execution of the instruction STAX B, 3A H will be stored in the memory location 2100 H. i.e. M = 3AH 2100H The combination STAX H is not included in this instruction as MOV A, M performs the same operation. 143XCHG (Exchange the contents of H-L register with D-E register) This is one byte instruction and no operand is needed with it. It exchanges the contents of H and L register with D and E registers respectively. i.e. H↔ D and L ↔ E For example: If H = 25 H , L = 32 H and D = 12 H, E = 1B H then after the execution of XCHG instruction, we have: H = 12 H, L = 1B H and D = 25 H, E = 32 H The instruction XCHG is generally used to keep track of more than one memory location at a time without using LDAX and STAX instructions. Let us write a program to add two numbers stored in memory locations 2100 H and 2201 H without using LDAX and STAX instructions. The answer is to be loaded in the memory location 2100 H. LXI H, 2201 H ; Loads H = 22 H and L = 01 H LXI D, 2100 H ; Loads D = 21 H and E = 00 H MOV A, M ; A ← M 2201H XCHG ; H = 21 H, L = 00 H and D = 22 H, E = 01 H ADD M ; A ← A+ M 2100H MOV M, A ; M ← A 2100H HLT In this program no LDAX and STAX instructions are used. DAA (Decimal Adjust the Accumulator) The DAA is one byte instruction and no operand is needed with this instruction. It adjusts the accumulator to packed BCD (Binary Coded Decimal) after addition of two BCDs. In other words, after addition of two hexadecimal numbers if this instruction is used then the result in decimal form is obtained. For this Auxiliary Carry Flag (AC) and Carry Flag (CY) take care of this instruction. It functions in two steps: 1. If the lower nibble (lower 4-bits) of the accumulator is greater than 9 or Auxiliary carry flag is set, then it adds 06 H to the accumulator. 2. Subsequently, if the higher nibble (higher 4-bits) of the accumulator is now greater than 9 or the carry flag (CY) is set, it adds 60 H to the accumulator. All the flags are affected with this instruction. Example 5.1 What will be the value of accumulator, CY and AC flags after the execution of the following program: MVI A, 38 H ADI 87 H DAA HLT Solution. A = 38 H 0 0 1 1 1 0 0 0 Adds 87 H 1 0 0 0 0 1 1 1 144

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