Lecture notes Electronic circuit analysis

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ANALOG ELECTRONICS CIRCUIT SL. NO. NAME OF THE CHAPTER PAGE NO. 1. Field Effect Transistor 2 2. Biasing Of BJTS 28 3. Biasing Of FETS And MOSFETS 47 4. Small Signal Analysis Of BJTS 58 5. Small Signal Analysis Of FETS 79 6. High Frequency Response Of FETS And BJTS 87 7. Feedback And Oscillators 94 8. Operational Amplifiers 116 9. Power Amplifiers 121 Page 1 Chapter 1 FIELD EFFECT TRANSISTORS 1.1 INTRODUCTION The field-effect transistor (FET) is a three-terminal device used for a variety of applications that match, to a large extent. Although there are important differences between the two types of devices, there are also many similarities. The primary difference between the two types of transistors is the fact that the BJT transistor is a current-controlled device as depicted in Fig. 1.1(a), while the JFET transistor is a voltage-controlled device as shown in Fig. 1.1(b). In other words, the current I in Fig. 1.1(a) is a direct function of the level of I . For the C B FET the current I will be a function of the voltage V applied to the input GS circuit as shown in Fig. 1.1(b). Fig. 1.1 (a) Current-controlled and (b) voltage-controlled amplifiers In each case the current of the output circuit is being controlled by a parameter of the input circuit—in one case a current level and in the other an applied voltage. Just as there are npn and pnp bipolar transistors, there are n-channel and p-channel field-effect transistors. However, it is important to keep in mind that the BJT transistor is a bipolar device—the prefix bi- revealing that the conduction level is a function of two charge carriers, electrons and holes. The FET is a unipolar device depending solely on either electron (n-channel) or hole (p-channel) conduction. The term field-effect in the chosen name deserves some explanation. For the FET an electric field is established by the charges present that will control the conduction path of the output circuit without the need for direct contact between the controlling and controlled quantities. Page 2 One of the most important characteristics of the FET is its high input impedance. At a level of 1 to several hundred mega ohms it far exceeds the typical input resistance levels of the BJT transistor configurations—a very important characteristic in the design of linear ac amplifier systems. On the other hand, the BJT transistor has a much higher sensitivity to changes in the applied signal. In other words, the variation in output current is typically a great deal more for BJTs than FETs for the same change in applied voltage. For this reason, typical ac voltage gains for BJT amplifiers are a great deal more than for FETs. In general, FETs are more temperature stable than BJTs, and FETs are usually smaller in construction than BJTs, making them particularly useful in integrated-circuit (IC) chips. The construction characteristics of some FETs, however, can make them more sensitive to handling than BJTs. Two types of FETs are there: the junction field-effect transistor (JFET) and the metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET category is further broken down into depletion and enhancement types. The MOSFET transistor has become one of the most important devices used in the design and construction of integrated circuits for digital computers. Its thermal stability and other general characteristics make it extremely popular in computer circuit design. 1.2 CONSTRUCTION AND CHARACTERISTICS OF JFETs The JFET is a three-terminal device with one terminal capable of controlling the current between the other two. The basic construction of the n-channel JFET is shown in Fig. 1.2. Note that the major part of the structure is the n-type material that forms the channel between the embedded layers of p-type material. The top of the n-type channel is connected through an ohmic contact to a terminal referred to as the drain (D), while the lower end of the same material is connected through an ohmic contact to a terminal referred to as the source (S). The two p-type materials are connected together and to the gate (G) terminal. In essence, therefore, the drain and source are connected to the ends of the n-type channel and the gate to the two layers of p-type material. In the absence of any applied potentials the JFET has two p-n junctions under no-bias conditions. The result is a depletion region at each junction as shown in Fig. 1.2 that resembles the same region of a diode under no-bias conditions. A depletion region is that region void of free carriers and therefore unable to support conduction through the region. The drain and source terminals are at opposite ends of the n-channel as introduced in Fig. 1.2 because the terminology is defined for electron flow. Page 3 Fig 1.2 Junction field-effect transistor (JFET) V = 0 V, V Some Positive Value GS DS In Fig. 1.3, a positive voltage V has been applied across the channel and the DS gate has been connected directly to the source to establish the condition V = 0 V. The result is a gate and source terminal at the same potential and a GS depletion region in the low end of each p-material similar to the distribution of the no-bias conditions of Fig. 1.2. The instant the voltage V (= V ) is applied, DD DS the electrons will be drawn to the drain terminal, establishing the conventional current I with the defined direction of Fig. 1.3. The path of charge flow clearly D reveals that the drain and source currents are equivalent (I = I ). Under the D S conditions appearing in Fig. 1.3, the flow of charge is relatively uninhibited and limited solely by the resistance of the n-channel between drain and source. Fig 1.3 JFET in the V = 0 V and V 0 V GS DS Page 4 As the voltage V is increased from 0 to a few volts, the current will increase as DS determined by Ohm’s law and the plot of I versus V will appear as shown in D DS Fig. 1.4. The relative straightness of the plot reveals that for the region of low values of V , the resistance is essentially constant. As V increases and DS DS approaches a level referred to as V in Fig. 1.4, the depletion regions of Fig. 1.3 P will widen, causing a noticeable reduction in the channel width. The reduced path of conduction causes the resistance to increase and the curve in the graph of Fig. 1.4 to occur. The more horizontal the curve, the higher the resistance, suggesting that the resistance is approaching “infinite” ohms in the horizontal region. Fig 1.4 I versus V for V =0 V D DS GS If V is increased to a level where it appears that the two depletion regions DS would “touch” as shown in Fig. 1.5, a condition referred to as pinch-off will result. The level of V that establishes this condition is referred to as the pinch- DS off voltage and is denoted by V as shown in Fig. 1.4. In actuality, the term P pinch-off suggests the current I is pinched off and drops to 0 A. As shown in D Fig. 1.4, I maintains a saturation level defined as I . In reality a very small D DSS channel still exists, with a current of very high density. The fact that I does not D drop off at pinch-off and maintains the saturation level indicated in Fig. 1.4 is verified by the following fact: The absence of a drain current would remove the possibility of different potential levels through the n-channel material to establish the varying levels of reverse bias along the p-n junction. The result would be a loss of the depletion region distribution that caused pinch-off in the first place. Page 5 Fig 1.5 Pinch-off (V = 0 V, V = V ) GS DS P As V is increased beyond V , the region of close encounter between the two DS P depletion regions will increase in length along the channel, but the level of I D remains essentially the same. In essence, therefore, once V = V the JFET has DS P the characteristics of a current source. As shown in Fig. 5.8, the current is fixed at I = I , but the voltage V (for levels V ) is determined by the applied D DSS DS P load. I is the maximum drain current for a JFET and is defined by the DSS conditions V = 0 V and V V . GS DS P Fig 1.6 Current source equivalent for V = 0 V, V V GS DS P VGS = 0 V The voltage from gate to source, denoted V , is the controlling voltage of the GS JFET. Just as various curves for I versus V were established for different C CE levels of I for the BJT transistor, curves of I versus V for various levels of B D DS V can be developed for the JFET. For the n-channel device the controlling GS voltage V is made more and more negative from its V = 0 V level. In other GS GS words, the gate terminal will be set at lower and lower potential levels as compared to the source. In Fig. 1.7 a negative voltage of -1 V has been applied between the gate and source terminals for a low level of V . The effect of the applied negative-bias DS Page 6 V is to establish depletion regions similar to those obtained with V = 0 V but GS GS at lower levels of V . Therefore, the result of applying a negative bias to the DS gate is to reach the saturation level at a lower level of V as shown in Fig. 1.8 DS for V = -1 V. GS Fig 1.7 Application of a negative voltage to the gate of a JFET The resulting saturation level for I has been reduced and in fact will continue D to decrease as V is made more and more negative. Note also on Fig. 1.8 how GS the pinch-off voltage continues to drop in a parabolic manner as V becomes GS more and more negative. Eventually, V when V = -V will be sufficiently GS GS P negative to establish a saturation level that is essentially 0 mA, and for all practical purposes the device has been “turned off.” In summary: The level of V that results in I = 0 mA is defined by V = V , with V GS D GS P P being a negative voltage for n-channel devices and a positive voltage for p- channel JFETs. Fig 1.8 n-Channel JFET characteristics with I = 8 mA and V = 4 V DSS P Page 7 The region to the right of the pinch-off locus of Fig. 1.8 is the region typically employed in linear amplifiers (amplifiers with minimum distortion of the applied signal) and is commonly referred to as the constant-current, saturation, or linear amplification region. Voltage-Controlled Resistor The region to the left of the pinch-off locus of Fig. 1.8 is referred to as the ohmic or voltage-controlled resistance region. In this region the JFET can actually be employed as a variable resistor (possibly for an automatic gain control system) whose resistance is controlled by the applied gate-to-source voltage. Note in Fig. 1.8 that the slope of each curve and therefore the resistance of the device between drain and source for V = V is a function of the applied DS P . As V becomes more and more negative, the slope of each curve voltage V GS GS becomes more and more horizontal, corresponding with an increasing resistance level. 2 r = r / 1- (V /V ) - (5.1) d 0 GS P where r is the resistance with V = 0 V and r the resistance at a particular o GS d level of V . GS P-Channel Devices The p-channel JFET is constructed in exactly the same manner as the n-channel device of Fig. 1.2, but with a reversal of the p- and n- type materials as shown in Fig. 1.9. Fig 1.9 p-Channel JFET Page 8 The defined current directions are reversed, as are the actual polarities for the voltages V and V . For the p-channel device, the channel will be constricted GS DS by increasing positive voltages from gate to source and the double-subscript notation for V will result in negative voltages for V on the characteristics of DS DS Fig. 1.10, which has an I of 6 mA and a pinch-off voltage of V = +6 V. Do DSS GS not let the minus signs for V confuse you. They simply indicate that the source DS is at a higher potential than the drain. Fig 1.10 p-Channel JFET characteristics with I = 6 mA and V = +6 V DSS P Note at high levels of V that the curves suddenly rise to levels that seem DS unbounded. The vertical rise is an indication that breakdown has occurred and the current through the channel (in the same direction as normally encountered) is now limited solely by the external circuit. Although not appearing in Fig. 1.8 for the n-channel device, they do occur for the n-channel device if sufficient voltage is applied. This region can be avoided if the level of V is noted on DSmax the specification sheet and the design is such that the actual level of V is less DS than this value for all values of V . GS Symbols The graphic symbols for the n-channel and p-channel JFETs are provided in Fig. 1.11. Note that the arrow is pointing in for the n-channel device of Fig. 1.11(a) to represent the direction in which I would flow if the p-n junction G were forward-biased. For the p-channel device (Fig. 1.11(b)) the only difference in the symbol is the direction of the arrow. Page 9 Fig 1.11 JFET symbols: (a) n-channel; (b) p-channel Summary • The maximum current is defined as I and occurs when V = 0 V DSS GS and VDS ≥ VP as shown in Fig. 1.12(a). • For gate-to-source voltages V less than (more negative than) the GS pinch-off level, the drain current is 0 A (I = 0 A) as appearing in D Fig. 1.12(b). • For all levels of V between 0 V and the pinch-off level, the current I GS D will range between I and 0 A, respectively, as reviewed by DSS Fig. 1.12(c). • For p-channel JFETs a similar list can be developed. Page 10 Fig 1.12 (a) V =0 V, I = I ; (b) cutoff (I = 0 A) V less than the pinch-off GS D DSS D GS level; (c) I exists between 0 A and I for V less than or equal to 0 V and D DSS GS greater than the pinch-off level. 1.3 TRANSFER CHARACTERISTICS For the BJT transistor the output current I and input controlling current I were C B related by beta, which was considered constant for the analysis to be performed. In equation form, I = f(I ) = βI -(1.2) C B B In Eq. (1.2) a linear relationship exists between I and I . Double the level of I C B B and I will increase by a factor of two also. C Unfortunately, this linear relationship does not exist between the output and input quantities of a JFET. The relationship between I and V is defined by D GS Shockley’s equation: 2 I = I (1- V /V ) -(1.3) D DSS GS P The squared term of the equation will result in a nonlinear relationship between I and V , producing a curve that grows exponentially with decreasing D GS magnitudes of V . GS The graphical approach, however, will require a plot of Eq. (1.3) to represent the device and a plot of the network equation relating the same variables. The solution is defined by the point of intersection of the two curves. It is important to keep in mind when applying the graphical approach that the device characteristics will be unaffected by the network in which the device is employed. The network equation may change along with the intersection between the two curves, but the transfer curve defined by Eq. (1.3) is unaffected. In general, therefore: The transfer characteristics defined by Shockley’s equation are unaffected by the network in which the device is employed. Page 11 The transfer curve can be obtained using Shockley’s equation or from the output characteristics of Fig. 1.8. In Fig. 1.13 two graphs are provided, with the vertical scaling in milli amperes for each graph. One is a plot of I versus V , D DS while the other is I versus V . Using the drain characteristics on the right of D GS the “y” axis, a horizontal line can be drawn from the saturation region of the curve denoted V = 0 V to the I axis. The resulting current level for both GS D graphs is I . The point of intersection on the I versus V curve will be as DSS D GS shown since the vertical axis is defined as V = 0 V. GS Fig 1.13 Obtaining the transfer curve from the drain characteristics In review: When V = 0 V, I = I . GS D DSS When V = V = -4 V, the drain current is zero milli amperes, defining another GS P point on the transfer curve. That is: When V = V , I = 0 mA. GS P D The drain characteristics relate one output (or drain) quantity to another output (or drain) quantity—both axes are defined by variables in the same region of the device characteristics. The transfer characteristics are a plot of an output (or drain) current versus an input-controlling quantity. There is therefore a direct “transfer” from input to output variables when employing the curve to the left of Fig. 1.13. If the relationship were linear, the plot of I versus V would result in D GS a straight line between I and V . However, a parabolic curve will result DSS P because the vertical spacing between steps of V on the drain characteristics of GS Fig. 1.13 decreases noticeably as V becomes more and more negative. GS Compare the spacing between V = 0 V and V = -1 V to that between GS GS V = -3 V and pinch-off. The change in V is the same, but the resulting GS GS change in I is quite different. D Page 12 Applying Shockley’s Equation The transfer curve of Fig. 1.13 can also be obtained directly from Shockley’s equation (1.3) given simply the values of I and V . The levels of I and V DSS P DSS P define the limits of the curve on both axes and leave only the necessity of finding a few intermediate plot points. Substituting V = 0 V in equation 1.3 gives, GS I = I -(1.4) D DSS VGS = 0v Substituting V = V yields, GS P I = 0V (1.5) D VGS = VP For the drain characteristics of Fig. 1.13, if we substitute V = -1 V, GS I = 4.5mA D as shown in Fig. 1.13. Note the care taken with the negative signs for V and GS in the calculations above. The loss of one sign would result in a totally V P erroneous result. It should be obvious from the above that given I and V (as is normally DSS P provided on specification sheets) the level of I can be found for any level of D V . Conversely, an equation for the resulting level of V for a given level of I GS GS D  V = V (1 -  ) (1.6) GS P  Shorthand Method I = I -(1.7) D DSS VGS = VP/2 V = 0.3V - (1.8) GS P ID = IDSS/2 Page 13 1.4 IMPORTANT RELATIONSHIPS Fig 1.14 (a) JFET versus (b) BJT A clear understanding of the impact of each of the equations above is sufficient background to approach the most complex of dc configurations. Recall that V BE = 0.7 V was often the key to initiating an analysis of a BJT configuration. Similarly, the condition I = 0 A is often the starting point for the analysis of a G JFET configuration. For the BJT configuration, I is normally the first parameter to be determined. B For the JFET, it is normally V . GS Page 14 1.5 DEPLETION-TYPE MOSFET There are two types of FETs: JFETs and MOSFETs. MOSFETs are further broken down into depletion type and enhancement type. The terms depletion and enhancement define their basic mode of operation, while the label MOSFET stands for metal-oxide-semiconductor-field-effect transistor. the depletion-type MOSFET, which happens to have characteristics similar to those of a JFET between cut-off and saturation at I but then has the added feature DSS of characteristics that extend into the region of opposite polarity for V . GS Basic Construction The basic construction of the n-channel depletion-type MOSFET is provided in Fig. 1.15. A slab of p-type material is formed from a silicon base and is referred to as the substrate. It is the foundation upon which the device will be constructed. In some cases the substrate is internally connected to the source terminal. However, many discrete devices provide an additional terminal labelled SS, resulting in a four-terminal device, such as that appearing in Fig. 1.15. The source and drain terminals are connected through metallic contacts to n-doped regions linked by an n-channel as shown in the figure. The gate is also connected to a metal contact surface but remains insulated from the n-channel by a very thin silicon dioxide (SiO ) layer. SiO is a particular type of insulator 2 2 referred to as a dielectric that sets up opposing electric fields within the dielectric when exposed to an externally applied field. Fig 1.15 n-Channel depletion-type MOSFET The fact that the SiO layer is an insulating layer reveals the following fact: 2 There is no direct electrical connection between the gate terminal and the channel of a MOSFET. Page 15 In addition: It is the insulating layer of SiO in the MOSFET construction that accounts 2 for the very desirable high input impedance of the device. In fact, the input resistance of a MOSFET is often that of the typical JFET, even though the input impedance of most JFETs is sufficiently high for most applications. The very high input impedance continues to fully support the fact that the gate current (I ) is essentially zero amperes for dc-biased G configurations. The reason for the label metal-oxide-semiconductor FET is now fairly obvious: metal for the drain, source, and gate connections to the proper surface—in particular, the gate terminal and the control to be offered by the surface area of the contact, the oxide for the silicon dioxide insulating layer, and the semiconductor for the basic structure on which the n- and p-type regions are diffused. The insulating layer between the gate and channel has resulted in another name for the device: insulated gate FET or IGFET, although this label is used less and less in current literature. Basic Operation and Characteristics In Fig. 1.16 the gate-to-source voltage is set to zero volts by the direct connection from one terminal to the other, and a voltage V is applied across DS the drain-to-source terminals. The result is an attraction for the positive potential at the drain by the free electrons of the n-channel and a current similar to that established through the channel of the JFET. In fact, the resulting current with VGS = 0 V continues to be labelled I , as shown in Fig. 1.17. DSS Fig 1.16 n-Channel depletion-type MOSFET with VGS = 0 V and an applied voltage V DD Page 16 Fig 1.17 Drain and transfer characteristics for an n-channel depletion-type MOSFET The region of positive gate voltages on the drain or transfer characteristics is often referred to as the enhancement region, with the region between cut-off and the saturation level of I referred to as the depletion region. Shockley’s DSS equation is applicable for the depletion-type MOSFET characteristics in both the depletion and enhancement regions. For both regions, it is simply necessary that the proper sign be included with V in the equation and the sign be GS carefully monitored in the mathematical operations. p-Channel Depletion-Type MOSFET The construction of a p-channel depletion-type MOSFET is exactly the reverse of that appearing in Fig. 1.15. There is an n-type substrate and a p-type channel, as shown in Fig. 1.18(a). The terminals remain as identified, but all the voltage polarities and the current directions are reversed, as shown in the same figure. The drain characteristics would appear exactly as in Fig. 1.16 but with V DS having negative values I having positive values as indicated (since the defined D direction is now reversed), and V having the opposite polarities as shown in GS Fig. 1.18(c). The reversal in V will result in a mirror image (about the I axis) GS D for the transfer characteristics as shown in Fig. 1.18(b). In other words, the drain current will increase from cut-off at V = V in the positive V region to GS P GS I and then continue to increase for increasingly negative values of V . DSS GS Shockley’s equation is still applicable and requires simply placing the correct sign for both V and V in the equation. GS P Page 17 Fig 1.18 p-Channel depletion-type MOSFET with I = 6 mA and V = -6 V DSS P Symbols The graphic symbols for an n- and p-channel depletion-type MOSFET are provided in Fig. 1.19. The lack of a direct connection (due to the gate insulation) between the gate and channel is represented by a space between the gate and the other terminals of the symbol. The vertical line representing the channel is connected between the drain and source and is “supported” by the substrate. Two symbols are provided for each type of channel to reflect the fact that in some cases the substrate is externally available while in others it is not. Page 18 Fig 1.19 Graphic symbols for (a) n-channel depletion-type MOSFETs and (b) p- channel depletion-type MOSFETs 1.6 ENHANCEMENT-TYPE MOSFET Although there are some similarities in construction and mode of operation between depletion-type and enhancement-type MOSFETs, the characteristics of the enhancement-type MOSFET are quite different from anything obtained thus far. The transfer curve is not defined by Shockley’s equation, and the drain current is now cut off until the gate-to-source voltage reaches a specific magnitude. In particular, current control in an n-channel device is now effected by a positive gate-to-source voltage rather than the range of negative voltages encountered for n-channel JFETs and n-channel depletion-type MOSFETs. Basic Construction The basic construction of the n-channel enhancement-type MOSFET is provided in Fig. 1.20. A slab of p-type material is formed from a silicon base and is again referred to as the substrate. As with the depletion-type MOSFET, the substrate is sometimes internally connected to the source terminal, while in other cases a fourth lead is made available for external control of its potential level. The source and drain terminals are again connected through metallic contacts to n-doped regions, but note in Fig. 1.20 the absence of a channel between the two n-doped regions. This is the primary difference between the construction of depletion-type and enhancement-type MOSFETs—the absence of a channel as a constructed component of the device. The SiO layer is still 2 present to isolate the gate metallic platform from the region between the drain and source, but now it is simply separated from a section of the p-type material. Page 19 In summary, therefore, the construction of an enhancement-type MOSFET is quite similar to that of the depletion-type MOSFET, except for the absence of a channel between the drain and source terminals. Fig 1.20 n-Channel enhancement-type MOSFET Basic Operation and Characteristics If V is set at 0 V and a voltage applied between the drain and source of the GS device of Fig. 1.20, the absence of an n-channel (with its generous number of free carriers) will result in a current of effectively zero amperes—quite different from the depletion-type MOSFET and JFET where I = I . It is not sufficient D DSS to have a large accumulation of carriers (electrons) at the drain and source (due to the n-doped regions) if a path fails to exist between the two. With V some DS positive voltage, V at 0 V, and terminal SS directly connected to the source, GS there are in fact two reverse-biased p-n junctions between the n-doped regions and the p-substrate to oppose any significant flow between drain and source. In Fig. 1.21 both V and V have been set at some positive voltage greater DS GS than 0 V, establishing the drain and gate at a positive potential with respect to the source. The positive potential at the gate will pressure the holes (since like charges repel) in the p-substrate along the edge of the SiO layer to leave the 2 area and enter deeper regions of the p-substrate, as shown in the figure. The result is a depletion region near the SiO insulating layer void of holes. 2 However, the electrons in the p-substrate (the minority carriers of the material) will be attracted to the positive gate and accumulate in the region near the surface of the SiO layer. The SiO layer and its insulating qualities will prevent 2 2 the negative carriers from being absorbed at the gate terminal. As V increases GS in magnitude, the concentration of electrons near the SiO surface increases 2 until eventually the induced n-type region can support a measurable flow between drain and source. The level of V that results in the significant GS Page 20

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