How 8051 microcontroller works

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1 8051 Architecture Overview 1.0 Introduction 2 1.1 Overview of 8051 Micro-controller 2 Ports, Address Latch Enable (ALE), Reset (RST), System Clock - Oscillator 1.2 On-Chip Memory Organization 5 General Purpose RAM, Bit-addressable RAM, Register Banks 1.3 Special Function Registers 11 Program Status Word, The B Register, Stack Pointer, Data Pointer, Parallel Input/Output Port Registers, Timer Registers, Serial Communication Registers, Interrupt Management Registers 1.4 Multiplexing Data and Address Bus 17 1.5 Tutorial Questions 19 2 Chapter 1 8051 Architecture Overview 1.0 Introduction In 1980, Intel introduced 8051, which is the first device in the MCS-51™ family of microcontroller, to the market. There are other second source suppliers of the ICs; these include Silicon Laboratories, Atmel, Philips, Dallas Semiconductor and several others. Intel 8051 has been around Though more than 20 years have passed since its introduction, the 8051 for over two decades but is is still as relevant today as it was in those days. In recent years some still very companies have incorporated many different features into the basic 8051 popular. chip and one such company is Silicon Laboratories. In 2000, Silicon Laboratories manufactured a field programmable, mixed signal chip (C8051F020) based on the 8051 core CPU. The chip is offered in different combinations of clock speed, FLASH and on-chip RAM size. They also offer different digital and analog peripherals such as: ♦ I/O ports ♦ Timers/Counters ♦ UARTs (Universal Asynchronous Receiver Transmitters) ♦ SPI and SMBus serial transceivers ♦ ADC/DAC (Analog-to-Digital Converters / Digital-to-Analog Converters) ♦ Temperature Sensor 1.1 Overview of 8051 Microcontroller TM These enhanced microcontrollers still use the MCS-51 basic set of machine instructions. The only differences that set them apart are the additional hardware features and the enhanced speed of operation. This section briefly describes the basic functions of the pins available. The internal features of the basic 8051 microcontroller can be seen in the block diagram shown in Figure 1.1. It is capable of addressing 64K of external program memory and a separate 64K of external data memory if required. Chapter 1 8051 Architecture Overview 3 T0 T1 /INT0 /INT1 Other interrupts 128 bytes Timer/Counter 4K byte Program Data Memory (Timer 0 & Memory (ROM) (RAM) Timer 1) 8051 CPU 64 K Bus I/O ports Serial Port Expansion Control Oscillator &Timing From Crystal Oscillator or RC ALE /PSEN P3 P2 P1 P0 TxD RxD (Address/data) network Figure 1.1 Block Diagram of the generic 8051 Microcontroller Ports The 8051 consists of 4 standard Ports (0, 1, 2, and 3). The ports are Intel 8051 has multi-purpose. In a minimum-component basic design without expansion, four multi- purpose they are used as general purpose I/O. For larger designs incorporating flexible ports external memory, the ports function as multiplexed address and data which are bit- and byte- buses. With careful hardware design and satisfying the timing addressable. requirements of 8051, the external memory can be easily and seamlessly made accessible to the programmer. In addition, the ports may be controlled by a digital peripheral, UART or external interrupts. The ports are both bit- and byte-addressable. For example, the pins of Port 0 are designated as P0.0, P0.1, P0.2, etc. Figure 1.2 shows the pin assignments of 8051. Address Latch Enable (ALE) The 8051 uses the ALE signal for demultiplexing the address and data bus (AD7-AD0) associated with external memory (see section 1.5). External memory is accessed in two phases delineated by the state of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are latched into an external register. When this is done, 4 Chapter 1 8051 Architecture Overview the port lines are available for data input or output. When ALE falls, signaling the beginning of the second phase, the address latch outputs remain fixed and are no longer dependent on the latch input. Later in the second phase, the Data Bus controls the state of the AD0:7 at the time /RD or /WR is asserted. 40 VCC XTL2 18 39 P0.0 AD0 XTL1 19 38 P0.1 AD1 37 P0.2 AD2 36 P0.3 AD3 35 P0.4 AD4 34 P0.5 AD5 RXD P3.0 10 33 P0.6 AD6 TXD P3.1 11 32 P0.7 AD7 /INT0 P3.2 12 P2.0 AD8 /INT1 P3.3 13 21 P2.1 AD9 T0 P3.4 14 22 8051 P2.2 AD10 23 T1 P3.5 15 P2.3 AD11 24 /WR P3.6 16 25 P2.4 AD12 /RD P3.7 17 P2.5 AD13 26 P2.6 AD14 27 RST 9 P2.7 AD15 28 /EA 31 1 P1.0 to to ALE 30 8 P1.7 20 /PSEN 29 VSS Figure 1.2 8051 pin assignment Reset (RST) Reset circuitry allows the 8051 to be easily placed in a predefined default condition. On entry to the reset state, the following occur: ♦ The MCU halts program execution ♦ Special Function Registers (SFRs) are initialized to their defined reset values ♦ External port pins are forced to a known state ♦ Interrupts and timers are disabled Sources of reset include Power-on Reset and External Reset. Chapter 1 8051 Architecture Overview 5 System Clock - Oscillator The 8051 features an on-chip oscillator that is typically driven by a crystal connected to XTAL1 and XTAL2 with two external stabilizing capacitors as shown in Figure 1.3. XTAL1 The on-chip oscillator needn’t be driven by a crystal; a TTL clock source XTAL2 will suffice. Figure 1.3 Schematic of the Oscillator The nominal crystal frequency is 12 MHz for most ICs in the MCS-51™ family. The on-chip oscillator needn’t be driven by a crystal; it can be replaced by a TTL clock source connected to XTAL1 instead. 1.2 On-Chip Memory Organization The 8051 has a limited on-chip program (code) and data memory space. Code and data However it has the capability of expanding to a maximum of 64K external memory may be expanded code memory and 64K external data memory when required. using external components. Program Memory (i.e. code memory can either be the on-chip ROM or an external ROM as shown in Figure 1.4. When /EA (External Access) pin is tied to +5 volts, it allows the program to be fetched from the internal 4K (0000H-0FFFH) ROM. If /EA is connected to ground, then all program fetches are directed to external ROM. In addition /PSEN is used as the read strobe to external ROM, while it is not activated for the internal program fetches. 6 Chapter 1 8051 Architecture Overview FFFFH 0FFFH 0FFFH /EA=0 /EA=1 External Internal 0000H 0000H /PSEN Figure 1.4 Program Memory Organization (Read Only) The Data Memory organization is shown in Figure 1.5. It depicts the internal and external Data Memory space available in 8051. Figures 1.6a and 1.6b show more details of the internal data memory (Read/Write memory or Random Access Memory) The Internal Data Memory space, as shown in Figure 1.5, is divided into three sections. They are referred to as the Lower 128, the Upper 128, and the SFR. In fact there are 384 physical bytes of memory space, though the Upper 128 and SFRs share the same addresses from location 80H to FFH. Appropriate instructions, using direct or indirect addressing modes, will access each memory block accordingly. Chapter 1 8051 Architecture Overview 7 External 0FFFFH Internal FFH Special Function Upper 128 Registers Indirect addressing Direct Addressing 80H 7FH Lower 128 /RD Direct/Indirect Addressing /WR 00H 0000H Figure 1.5 Internal & External Data memory (Random Access Memory) Organization As shown in Figure 1.6a and 1.6b, the internal data memory space is divided into register banks (00H-1FH), bit-addressable RAM (20H-2FH), general purpose RAM (30H-7FH), and special function registers (80H- FFH). In the Lower 128 bytes of RAM, 4 banks of 8 registers each are available to the user. The 8 registers are named R0 through R7. By programming two bits in the Program Status Word (PSW), an appropriate register bank can be selected. In the Special Function Register (SFR) block (Figure 1.6b) registers which have addresses ending with OH or 8H are byte- as well as bit- addressable. Some registers are not bit-addressable at all. For example, the Stack Pointer Register (SP) and Data Pointer Register (DPTR) are not bit-addressable. 8 Chapter 1 8051 Architecture Overview Byte Bit Address Address 7F General Purpose RAM 30 B 2F 7F 7E 7D 7C 7B 7A 79 78 i 2E 77 76 75 74 73 72 71 70 t 2D 6F 6E 6D 6C 6B 6A 69 68 2C 67 66 65 64 63 62 61 60 A 2B 5F 5E 5D 5C 5B 5A 59 58 d 2A 57 56 55 54 53 52 51 50 d 29 4F 4E 4D 4C 4B 4A 49 48 r 28 47 46 45 44 43 42 41 40 e 27 3F 3E 3D 3C 3B 3A 39 38 s 26 37 36 35 34 33 32 31 30 s 25 2F 2E 2D 2C 2B 2A 29 28 a 24 27 26 25 24 23 22 21 20 b 23 1F 1E 1D 1C 1B 1A 19 18 l 22 17 16 15 14 13 12 11 10 e 21 0F 0E 0D 0C 0B 0A 09 08 20 07 06 05 04 03 02 01 00 1F Bank 3 18 17 Bank 2 10 0F Bank 1 08 07 Default Register Bank for R0 – R7 00 Figure 1.6a Summary of 8051 on-chip Data Memory (Register Banks and RAM) Chapter 1 8051 Architecture Overview 9 Byte Bit Address Address FF F0 F7 F6 F5 F4 F3 F2 F1 F0 B E0 E7 E6 E5 E4 E3 E2 E1 E0 ACC D0 D7 D6 D5 D4 D3 D2 - D0 PSW - B8 - - BC BB BA B9 B8 IP B0 B7 B6 B5 B4 B3 B2 B1 B0 P3 A8 AF - - AC AB AA A9 A8 IE A0 A7 A6 A5 A4 A3 A2 A1 A0 P2 99 Not bit-addressable SBUF 98 9F 96 95 94 93 92 91 90 SCON 90 97 96 95 94 93 92 91 90 P1 8D Not bit-addressable TH1 8C Not bit-addressable TH0 8B Not bit-addressable TL1 8A Not bit-addressable TL0 89 Not bit-addressable TMOD 88 8F 8E 8D 8C 8B 8A 89 88 TCON 87 Not bit-addressable PCON 83 Not bit-addressable DPH 82 Not bit-addressable DPL 81 Not bit-addressable SP 80 87 86 85 84 83 82 81 80 P0 Figure 1.6b Summary of 8051 on-chip data Memory (Special Function Registers) 10 Chapter 1 8051 Architecture Overview General Purpose RAM There are 80 bytes of general purpose RAM from address 30H to 7FH. The bottom 32 bytes from 00H to 2FH can be used as general purpose RAM too, although these locations have other specific use also. Any location in the general Any location in the general purpose RAM can be accessed freely using purpose RAM can be the direct or indirect addressing modes. For example, to read the accessed freely using contents of internal RAM address 62H into the accumulator A, the the direct or following instruction could be used: indirect addressing modes. MOV A,62H The above instruction uses direct addressing and transfers a byte of data from location 62H (source) to the accumulator (destination). The destination for the data is implicitly specified in the instruction op-code as the accumulator (A). Addressing modes are discussed in details in Chapter 3 (Instruction Set). Internal RAM can also be accessed using indirect addressing through R0 or R1. The following two instructions perform the same operation as the single instruction above: MOV R1,62H MOV A,R1 The first instruction uses immediate addressing to transfer the value 62H into register R1. The second instruction uses indirect addressing to transfer the data “pointed to by R1” into the accumulator. Bit-addressable RAM There are 128 general purpose bit-addressable locations at byte addresses 20H through 2FH. For example, to clear bit 78H, the following instructions could be used: CLR 78H Referring to Figure 1.6a, note that “bit address 78H” is the least significant bit (bit 0) at “byte address 2FH”. The instruction has no effect on the other bits at this address. The same operation can also be performed as follows: Chapter 1 8051 Architecture Overview 11 MOV A,2FH ANL A,11111110B MOV 2FH,A Another alternative is to use the following instruction: CLR 2F.0H Register Banks The bottom 32 locations of the internal memory, from location 00H to 1FH, contain the register banks. The 8051 instruction set supports 8 registers, R0 through R7. After a system reset these registers are at addresses 00H to 07H. The following instruction reads the contents of address 04H into the accumulator A: MOV A,R4 ;this is a 1 byte instruction using ;register addressing mode The same operation can be performed using the following instruction: MOV A,04H ;this is a 2-byte instruction using ;direct addressing mode Instructions using registers R0 to R7 are shorter than the equivalent instructions using direct addressing. Thus the data items used frequently in a program should use one of these registers to speed up the program execution. 1.3 Special Function Registers The 8051 internal registers are configured as part of the on-chip RAM. SFRs are Hence each of these registers also has a memory address. There are 21 generally accessed special function registers (SFRs) at the top of the internal RAM, from using direct addressing. addresses 80H to FFH (see Figure 1.6b). Some SFRs are both bit- Most SFRs are accessed using direct addressing. Some SFRs are both and byte- bit-addressable and byte-addressable. For example, the instructions addressable. SETB 0D3H SETB 0D4H 12 Chapter 1 8051 Architecture Overview set bit 3 and 4 in the Program Status Word (PSW.3 and PSW.4), leaving the other bits unchanged. This will select Bank 3 for registers R0 to R7 at address locations 18H to 1FH. Since the SETB instruction operates on bits (not bytes), only the addressed bit is affected. Program Status Word The program status word (PSW) at address D0H and contains the status bits as shown in Table 1.1. Bit Symbol Bit Address Description PSW.7 CY D7H Carry flag PSW.6 AC D6H Auxiliary carry flag PSW.5 F0 D5H User Flag 0 PSW.4 RS1 D4H Register bank select 1 Register bank select 0 00 = bank 0; address 00H-07H PSW.3 RS0 D3H 01 = bank 1; address 08H-0FH 10 = bank 2; address 10H-17H 11 = bank 3; address 18H-1FH PSW.2 OV D2H Overflow flag PSW.1 - D1H Reserved PSW.0 P D0H Even parity flag Table 1.1 Summary of PSW Register bits Carry Flag (CY) The carry flag (CY) has a dual purpose. It is used in the traditional way for arithmetic operations – it is set if there is a carry out of bit 7 during an addition operation or set if there is a borrow into bit 7 during a subtraction operation. For example, if accumulator A=F1H, then the instruction ADD A,15 leaves a value of 00H in the accumulator and sets the carry flag in PSW (PSW.7). The carry flag is extensively used as a 1-bit register in Boolean operations on bit-valued data. For example, the following instruction Chapter 1 8051 Architecture Overview 13 ANDs bit 38H with the carry flag and places the result back in the carry flag: ANL C,038H Auxiliary Carry Flag (AC) When adding binary coded decimal (BCD) values, the auxiliary carry flag (AC) is set if a carry was generated out of bit 3 into bit 4 or if the result in the lower nibble is in the range 0AH to 0FH. For example, the following instruction sequence will result in the auxiliary carry flag being set. MOV R0,2 MOV A,8 ADD A,R0 User Flag 0 (F0) This is a general purpose flag bit available for user applications. Register Bank Select Bits (RS1 and RS0) The register bank select bits, RS0 and RS1, determine the active register bank. They are cleared after reset (so Bank 0 is selected by default) and are changed by the application program as required. For example, the following instruction sequence enables register Bank 3 then moves the contents of register R0 (byte address 18H, see Figure 1.6a) to the accumulator: SETB RS1 ;alternatively use instruction ;SETB 0D4H SETB RS0 ;alternatively use instruction ;SETB 0D3H MOV A,R0 Overflow Flag (OV) The overflow flag (OV) is set after an addition or subtraction operation if there is an arithmetic overflow (the result is out of range for the data size). When signed numbers are added or subtracted, a program can 14 Chapter 1 8051 Architecture Overview test this bit to determine if the result is in the proper range. For 8-bit signed numbers, the result should be in the range of +127 to –128). Even Parity Flag (P) The number of ‘1’ bits in the accumulator plus the parity bit (P) is always even. The parity bit is automatically set or cleared to establish even parity with the accumulator. For example, if the accumulator contains 00101100B then P is set to 1. P is reset to 0 if the accumulator contains even number of 1s. The B Register The B register, or accumulator B, is at address F0H and is used along with the accumulator for multiplication and division operations. For example: MOV A,9 MOV B,5 MUL AB ;9 x 5 = 45 or 2DH, B=0, A=2DH MOV A,99 MOV B,5 MUL AB ;99 x 5 = 495 or 1EFH, B=1, A=EFH MOV A,10 MOV B,5 DIV AB ;10/5 = 2, Remainder=0 , B=0, A=2 MOV A,99 MOV B,5 DIV AB ;99/5=19(13H),Remainder=4,B=4,A=13H The B register can also be used as a general purpose register. It is bit- addressable through bit address F0H to F7H. Stack Pointer The stack pointer (SP) is an 8-bit register and is located at address 81H. Stack operations include “pushing” data on the stack and “popping” data off the stack. Each time data is pushed on to the stack, SP is Chapter 1 8051 Architecture Overview 15 incremented. Popping from the stack reads data out and SP is decremented. For example if SP=6FH and ACC=20H, after pushing the accumulator content onto the stack, SP becomes 70H as shown in Figure 1.7. MOV A,20H MOV SP,6FH PUSH ACC SP=6FH before PUSH Æ 6FH XX After PUSH ACC, SP=70H Æ 70H 20H . . . Figure 1.7 Memory snap-shot of the Stack Data Pointer The data pointer register (DPTR) is used to access external code or data memory. It is a 16-bit register located at addresses 82H (DPL, low byte) and 83H (DPH, high byte). The following instructions load 5AH into the external RAM location 1040H. MOV A,5AH MOV DPTR,1040H MOVX DPTR,A The first instruction uses immediate addressing to load the data constant 5AH into the accumulator. The second instruction also uses immediate addressing to load the 16-bit address constant 1040H into the data pointer. The third instruction uses indirect addressing to move the value in A (i.e. 5AH) to the external RAM location whose address is in the DPTR register (i.e. 1040H). The “X” in the mnemonic “MOVX” indicates that the move instruction accesses external data memory. 16 Chapter 1 8051 Architecture Overview Parallel Input/Output Port Registers The 8051 I/O ports consist of Port 0 located at address 80H, Port 1 at address 90H, Port 2 at address A0H and Port 3 is located at address B0H. All the ports are bi-directional. Besides being used as general input/output lines, Port 0 and 2 can be used to form the 16-bit address in Bit- addressable order to interface with the external memory, with Port 0 being the low ports of 8051 byte of the address and the Port 2 outputting the high byte of the provide powerful address. Similarly port 3 pins have alternate functions of serving as interfacing possibilities. interrupt and timer inputs, serial port inputs and outputs, as well as RD and WR lines for external Data Memory. All the ports are bit-addressable and thus provide powerful interfacing possibilities. For example, if a Light Emitting Diode (LED) is connected through an appropriate driver to Port 1 bit 5, it could be turned on and off using the following instructions- SETB P1.5 will turn the LED on, and CLR P1.5 will turn it off. These instructions use the dot operator to address a bit of Port 1. However, the following instruction can also be used: CLR 95H ; same as CLR P1.5 Timer Registers The 8051 The basic 8051 contains two 16-bit timer/counters for timing intervals or contains two 16-bit counting events. Timer 0 is located at addresses 8AH (TL0, low byte) timer/counters and 8CH (TH0, high byte) and Timer 1 is located at addresses 8BH (TL1, for timing intervals and low byte) and 8DH (TH1, high byte). The Timer Mode register (TMOD), counting events. which is located at address 89H, and the Timer Control register (TCON), which is located at address 88H, are used to program the timer operations. Only TCON is bit-addressable. Timer operations and programming details of C8051F020 are discussed in Chapter 8. Chapter 1 8051 Architecture Overview 17 Serial Communication Registers The 8051 contains an on-chip serial port for communication with serial devices such as modems or for interfacing with other peripheral devices with a serial interface (A/D converters, RF/IR transmitters, etc). The Serial Data Buffer register (SBUF) located at address 99H holds both the transmit data and the receive data. Writing to SBUF loads data for transmission while reading SBUF returns the received data. Various modes of operation are programmable through the bit-addressable Serial port Control register (SCON), which is located at address 98H. Serial communication issues for C8051F020 are discussed in detail in Chapter 10. Interrupt Management Registers The 8051 has 5 interrupt sources which include 2 external interrupts, 2 timer interrupts and a serial port interrupt. Each interrupt can be individually enabled or disabled by writing a ‘1’ or a ‘0’ respectively into the Interrupt Enable register (IE). The bit 7 of the register is a global enable bit, which if cleared, will disable all interrupts. In addition, each interrupt source can be set to either one of the two priority levels i.e. High or Low. This is done through the Interrupt Priority register (IP), which is located at address B8H. Interrupts for C8051F020 are discussed in detail in Chapter 11. 1.4 Multiplexing Address and Data Bus In order to save pins and accommodate other functions, the 8051 was designed with multiplexed address and data buses in mind. It reduces the separate 16 address and 8 data lines to a combined 16 lines of address and data. The multiplexed mode operates by latching the low byte of the address using the ALE signal during the first half of each memory cycle. A 74HC373 (or equivalent) latch holds the low byte of the address stable for the duration of the memory cycle. During the second half of the memory cycle, data is read from or written to the data bus. 18 Chapter 1 8051 Architecture Overview Figure 1.8a shows the normal write cycle in the execution of a 8051 instruction. Figure 1.8b shows the hardware connection to de-multiplex the address and data lines to allow for external memory access. Memory Cycle A8-A15 Address ALE AD0-AD7 Address Data /WR Figure 1.8a Write cycle of 8051 instruction D0 D7 8051 74LS373 AD0 A0 P0.0 Latch AD7 P0.7 A7 EL /OE ALE P2.0 A8 A15 P2.7 /WR Figure 1.8b Hardware connection to de-multiplex the address and data bus Chapter 1 8051 Architecture Overview 19 1.5 Tutorial Questions 1. What instruction sequence could be used to read bit 1 of Port 0 and write the state of the bit read to bit 0 of Port 2? 2. Illustrate an instruction sequence to store the value of 8AH in external RAM at address 3CB0H. 3. Write an instruction to initialize the stack pointer to create a 32- byte stack at the top of the memory of 8051. 4. What is the bit address of bit 2 in the byte address 2BH in the 8051’s internal data memory? 5. What is the bit address of the most significant bit in the byte address 2DH in the 8051’s internal data memory? 6. What is the state of the Parity Flag in the PSW after the execution of each of the following instructions? (a) MOV A, 0F1H (b) MOV A, 0CH

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