# Lecture notes on Computer Arithmetic

###### what is computer arithmetic in computer architecture, how computer can perform arithmetic on-binary numbers and what is an arithmetic operator computer programming
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Published Date:23-07-2017
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Computer Organization and Architecture Chapter 5 : Computer Arithmetic Chapter – 5 Computer Arithmetic Integer Representation: (Fixed-point representation): An eight bit word can be represented the numbers from zero to 255 including 00000000 = 0 00000001 = 1 - - - - - - - 11111111 = 255 In general if an n-bit sequence of binary digits a , a …..a , a ; is interpreted as unsigned n-1 n-2 1 0 integer A. n1 i A = 2 a  i i0 Sign magnitude representation: There are several alternative convention used to represent negative as well as positive integers, all of which involves treating the most significant (left most) bit in the word as sign bit. If the sign bit is 0, the number is +ve and if the sign bit is 1, the number is –ve. In n bit word the right most n-1 bit hold the magnitude of integer. For an example, +18 = 00010010 - 18 = 10010010 (sign magnitude) The general case can be expressed as follows: n2 i A = if a = 0 n-1  2 a i i0 n2 i = - if a =1 2 a n-1  i i0 n2 n-1 i A = -2 a + n-1 2 a (Both for +ve and –ve)  i i0 There are several drawbacks to sign-magnitude representation. One is that addition or subtraction requires consideration of both signs of number and their relative magnitude to carry out the required operation. Another drawback is that there are two representation of zero. For an example: +0 = 00000000 10 -0 = 10000000 this is inconvenient. 10 2’s complement representation: Like sign magnitude representation, 2’s complement representation uses the most significant bit as sign bit making it easy to test whether the integer is negative or positive. It differs from the use of sign magnitude representation in the way that the other bits are interpreted. For negation, take the Boolean complement (1’s complement) of each bit of corresponding positive number, and then add one to the resulting bit pattern viewed as unsigned integer. Consider n bit integer A in 2’s complement representation. If A is +ve then the sign bit a is zero. The remaining bits n-1 represent the magnitude of the number. Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 1 Computer Organization and Architecture Chapter 5 : Computer Arithmetic n2 i A = for A ≥ 0 2 a  i i0 The number zero is identified as +ve and therefore has zero sign bit and magnitude of all 0’s. We can see that the range of +ve integer that may be represented is from 0 (all the magnitude bits n-1 are zero) through 2 -1 (all of the magnitude bits are 1). Now for –ve number integer A, the sign bit a is 1. The range of –ve integer that can be n-1 n-1 represented is from -1 to -2 n2 n-1 i 2’s complement, A = -2 a + n-1 2 a  i i0 Defines the twos complement of representation of both positive and negative number. For an example: +18 = 00010010 1’s complement = 11101101 2’s complement = 11101110 = -18 5.1 Addition Algorithm 5.2 Subtraction Algorithm 1001 = -7 1100 = -4 0011 = 3 0101 = +5 0100 = +4 0100= 4 1110 =-2 10000 = 0 0111= 7 (a) (-7)+(+5) (b) (-4)+(4) (c) (+3)+(+4) 1100 = -4 0101 =5 1001 = -7 1111 = -1 0100 =4 1010 = -6 11011 = -5 1001=overflow 10011 = overflow (d) (-4)+(-1) (e) (+5)+(+4) (f) (-7)+(-6) The first four examples illustrate successful operation if the result of the operation is +ve then we get +ve number in ordinary binary notation. If the result of the operation is –ve we get negative number in twos complement form. Note that in some instants there is carry bit beyond the end of what which is ignored. On any addition the result may larger then can be held in word size being use. This condition is called over flow. When overflow occur ALU must signal this fact so that no attempt is made to use the result. To detect overflow the following rule observed. If two numbers are added, and they are both +ve or both –ve; then overflow occurs if and only if the result has the opposite sign. The data path and hardware elements needed to accomplish addition and subtraction is shown in figure below. The central element is binary adder, which is presented two numbers for addition and produces a sum and an overflow indication. The binary adder treats the two numbers as unsigned integers. For addition, the two numbers are presented to the adder from two registers A and B. The result may be stored in one of these registers or in the third. The overflow indication is stored in a 1-bit overflow flag V (where 1 = overflow and 0 = no overflow). For subtraction, the subtrahend (B register) is passed through a 2’s complement unit so that its 2’s complement is presented to the adder (a – b = a + (-b)). Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 2 / Computer Organization and Architecture Chapter 5 : Computer Arithmetic B Register A Register Complement Switch B 7 XOR n bit Adder B 8 V Z S C n bit B 7 Check for Zero Fig: Block diagram of hardware for addition / subtraction 5.3 Multiplication Algorithm The multiplier and multiplicand bits are loaded into two registers Q and M. A third register A is initially set to zero. C is the 1-bit register which holds the carry bit resulting from addition. Now, the control logic reads the bits of the multiplier one at a time. If Q is 1, the multiplicand is added 0 to the register A and is stored back in register A with C bit used for carry. Then all the bits of CAQ are shifted to the right 1 bit so that C bit goes to A , A goes to Q and Q is lost. If Q is n-1 0 n-1 0 0 0, no addition is performed just do the shift. The process is repeated for each bit of the original multiplier. The resulting 2n bit product is contained in the QA register. Fig: Block diagram of multiplication Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 3 Computer Organization and Architecture Chapter 5 : Computer Arithmetic There are three types of operation for multiplication.  It should be determined whether a multiplier bit is 1 or 0 so that it can designate the partial product. If the multiplier bit is 0, the partial product is zero; if the multiplier bit is 1, the multiplicand is partial product.  It should shift partial product.  It should add partial product. Unsigned Binary Multiplication 1011 Multiplicand 11 X 1101 Multiplier 13 1011 0000 Partial Product 1011 + 1011 10001111 Product (143) Start M ß Multiplicand, Q ß Multiplier C, A ß 0, Count ß No. of bits of Q Is Yes No Q = 1 A ß A + M 0 ? Right Shift C, A, Q Count ß Count - 1 Is No Count = 0 ? Yes Stop Result in AQ Fig. : Flowchart of Unsigned Binary Multiplication Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 4 Computer Organization and Architecture Chapter 5 : Computer Arithmetic Example: Multiply 15 X 11 using unsigned binary method C A Q M Count Remarks 0 0000 1011 1111 4 Initialization 0 1111 1011 - - Add (A ß A + M) 0 0111 1101 - 3 Logical Right Shift C, A, Q 1 0110 1101 - - Add (A ß A + M) 0 1011 0110 - 2 Logical Right Shift C, A, Q 0 0101 1011 - 1 Logical Right Shift C, A, Q 1 0100 1011 - - Add (A ß A + M) 0 1010 0101 - 0 Logical Right Shift C, A, Q 7 5 2 0 Result = 1010 0101 = 2 + 2 + 2 + 2 = 165 Alternate Method of Unsigned Binary Multiplication Start X ß Multiplicand, Y ß Multiplier Sum ß 0, Count ß No. of bits of Y Is Yes No Y = 1 Sum ß Sum + X 0 ? Left Shift X, Right Shift Y Count ß Count - 1 Is No Count = 0 ? Yes Stop Result in Sum Fig: Unsigned Binary Multiplication Alternate method Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 5 Computer Organization and Architecture Chapter 5 : Computer Arithmetic Algorithm: Step 1: Clear the sum (accumulator A). Place the multiplicand in X and multiplier in Y. Step 2: Test Y if it is 1, add content of X to the accumulator A. 0; Step 3: Logical Shift the content of X left one position and content of Y right one position. Step 4: Check for completion; if not completed, go to step 2. Example: Multiply 7 X 6 Sum X Y Count Remarks 000000 000111 110 3 Initialization 000000 001110 011 2 Left shift X, Right Shift Y 001110 011100 001 1 Sum ß Sum + X, Left shift X, Right Shift Y 101010 111000 000 0 Sum ß Sum + X, Left shift X, Right Shift Y 5 3 1 Result = 101010 = 2 + 2 + 2 = 42 Signed Multiplication (Booth Algorithm) – 2’s Complement Multiplication Multiplier and multiplicand are placed in Q and M register respectively. There is also one bit register placed logically to the right of the least significant bit Q of the Q register and designated 0 as Q . The result of multiplication will appear in A and Q resister. A and Q are initialized to -1 -1 zero if two bits (Q and Q ) are the same (11 or 00) then all the bits of A, Q and Q registers are 0 -1 -1 shifted to the right 1 bit. If the two bits differ then the multiplicand is added to or subtracted from the A register depending on weather the two bits are 01 or 10. Following the addition or subtraction the arithmetic right shift occurs. When count reaches to zero, result resides into AQ n-1 n-2 1 0 in the form of signed integer -2 a + 2 a + …………… + 2 a + 2 a . n-1 n-2 1 0 Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 6 Computer Organization and Architecture Chapter 5 : Computer Arithmetic Start Initialize A ß 0, Q ß 0, -1 M ß Multiplicand, Q ß Multiplier, Count ß No. of bits of Q Is = 01 = 10 A ß A - M Q Q A ß A + M 0 -1 ? = 11 = 00 Arithmetic Shift Right A, Q, Q-1 Count ß Count - 1 Is No Count = 0 ? Yes Stop Result in AQ Fig.: Flowchart of Signed Binary Numbers (using 2’s Complement, Booth Method) Example: Multiply 9 X -3 = -27 using Booth Algorithm +3 = 00011, -3 = 11101 (2’s complement of +3) A Q Q Add (M) Count Remarks -1 Sub ( M +1) 00000 11101 0 01001 10111 5 Initialization 10111 11101 0 - - - Sub (A ß A - M) as Q Q = 10 0 -1 11011 11110 1 - - 4 Arithmetic Shift Right A, Q, Q -1 00100 11110 1 - - - Add (A ß A + M) as Q Q = 01 0 -1 00010 01111 0 - - 3 Arithmetic Shift Right A, Q, Q -1 11001 01111 0 - - - Sub (A ß A - M) as Q Q = 10 0 -1 11100 10111 1 - - 2 Arithmetic Shift Right A, Q, Q -1 11110 01011 1 - - 1 Arithmetic Shift Right A, Q, Q -1 as Q Q = 11 0 -1 11111 00101 1 - - 0 Arithmetic Shift Right A, Q, Q -1 as Q Q = 11 0 -1 9 8 7 6 5 2 0 Result in AQ = 11111 00101 = -2 +2 +2 +2 +2 +2 +2 = -512+256+128+64+32+4+1 = -27 Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 7 Computer Organization and Architecture Chapter 5 : Computer Arithmetic 5.4 Division Algorithm Division is somewhat more than multiplication but is based on the same general principles. The operation involves repetitive shifting and addition or subtraction. First, the bits of the dividend are examined from left to right, until the set of bits examined represents a number greater than or equal to the divisor; this is referred to as the divisor being able to divide the number. Until this event occurs, 0s are placed in the quotient from left to right. When the event occurs, a 1 is placed in the quotient and the divisor is subtracted from the partial dividend. The result is referred to as a partial remainder. The division follows a cyclic pattern. At each cycle, additional bits from the dividend are appended to the partial remainder until the result is greater than or equal to the divisor. The divisor is subtracted from this number to produce a new partial remainder. The process continues until all the bits of the dividend are exhausted. Shift Left A A………… A Q………… Q n n-1 0 n-1 0 Add / Subtract Control Unit N+1 Bit Adder 0 M………… M Divisor n-1 0 Fig.: Block Diagram of Division Operation Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 8 Computer Organization and Architecture Chapter 5 : Computer Arithmetic Restoring Division (Unsigned Binary Division) Algorithm: Step 1: Initialize A, Q and M registers to zero, dividend and divisor respectively and counter to n where n is the number of bits in the dividend. Step 2: Shift A, Q left one binary position. Step 3: Subtract M from A placing answer back in A. If sign of A is 1, set Q to zero and add M 0 back to A (restore A). If sign of A is 0, set Q to 1. 0 Step 4: Decrease counter; if counter 0, repeat process from step 2 else stop the process. The final remainder will be in A and quotient will be in Q. Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 9 Computer Organization and Architecture Chapter 5 : Computer Arithmetic Example: Divide 15 (1111) by 4 (0100) A Q M Count Remarks M +1 00000 1111 00100 11100 4 Initialization 00001 111□ - - - Shift Left A, Q 11101 111□ - - - Sub (A ß A – M) 00001 1110 - - 3 Q ß 0, Add (Aß A + M) 0 00011 110□ - - - Shift Left A, Q 11111 110□ - - - Sub (A ß A – M) 00011 1100 - - 2 Q ß 0, Add (Aß A + M) 0 00111 100□ - - - Shift Left A, Q 00011 100□ - - - Sub (A ß A – M) 00011 1001 - - 1 Set Q ß 1 0 00111 001□ - - - Shift Left A, Q 00011 001□ - - - Sub (A ß A – M) 00011 0011 - - 0 Set Q ß 1 0 Quotient in Q = 0011 = 3 Remainder in A = 00011 = 3 Non – Restoring Division (Signed Binary Division) Algorithm Step 1: Initialize A, Q and M registers to zero, dividend and divisor respectively and count to number of bits in dividend. Step 2: Check sign of A; If A 0 i.e. b is 1 n-1 a. Shift A, Q left one binary position. b. Add content of M to A and store back in A. If A ≥ 0 i.e. b is 0 n-1 a. Shift A, Q left one binary position. b. Subtract content of M to A and store back in A. Step 3: If sign of A is 0, set Q to 1 else set Q to 0. 0 0 Step 4: Decrease counter. If counter 0, repeat process from step 2 else go to step 5. Step 5: If A ≥ 0 i.e. positive, content of A is remainder else add content of M to A to get the remainder. The quotient will be in Q. Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 10 Computer Organization and Architecture Chapter 5 : Computer Arithmetic Start Initialize: A ß 0, M ß Divisor, Q ß Dividend, Count ß No. of bits of Q Is Yes No Left Shift AQ A 0 Left Shift AQ ? A ß A + M A ß A - M Is No Yes Q ß 1 A 0 Q ß 0 0 0 ? Count ß Count - 1 Is Yes Count 0 ? No Is Yes No A 0 A ß A + M ? Quotient in Q Remainder in A Stop Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 11 Computer Organization and Architecture Chapter 5 : Computer Arithmetic Example: Divide 1110 (14) by 0011 (3) using non-restoring division. A Q M Count Remarks M +1 00000 1110 00011 11101 4 Initialization 00001 110□ - - - Shift Left A, Q 11110 110□ - - - Sub (A ß A – M) 11110 1100 - - 3 Set Q to 0 0 11101 100□ - - - Shift Left A, Q 00000 100□ - - - Add (A ß A + M) 00000 1001 - - 2 Set Q to 1 0 00001 001□ - - - Shift Left A, Q 11110 001□ - - - Sub (A ß A – M) 11110 0010 - - 1 Set Q to 0 0 11100 010□ - - - Shift Left A, Q 11111 010□ - - - Add (A ß A + M) 11111 0100 - - 0 Set Q to 0 0 00010 0100 - - - Add (A ß A + M) Quotient in Q = 0011 = 3 Remainder in A = 00010 = 2 Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 12 Computer Organization and Architecture Chapter 5 : Computer Arithmetic Floating Point Representation The floating point representation of the number has two parts. The first part represents a signed fixed point numbers called mantissa or significand. The second part designates the position of the decimal (or binary) point and is called exponent. For example, the decimal no + 6132.789 is represented in floating point with fraction and exponent as follows. Fraction Exponent +0.6132789 +04 +4 This representation is equivalent to the scientific notation +0.6132789 × 10 ±E The floating point is always interpreted to represent a number in the following form ±M × R . Only the mantissa M and the exponent E are physically represented in the register (including their sign). The radix R and the radix point position of the mantissa are always assumed. A floating point binary no is represented in similar manner except that it uses base 2 for the exponent. For example, the binary no +1001.11 is represented with 8 bit fraction and 0 bit exponent as follows. 100 0.1001110 × 2 Fraction Exponent 01001110 000100 The fraction has zero in the leftmost position to denote positive. The floating point number is E +4 equivalent to M × 2 = +(0.1001110) × 2 2 Floating Point Arithmetic The basic operations for floating point arithmetic are Floating point number Arithmetic Operations XE XE-YE YE X = Xs × B X + Y = (Xs × B + Ys) × B YE XE-YE YE Y = Ys × B X - Y = (Xs × B - Ys) × B XE+YE X Y = (Xs × Ys) × B XE-YE X / Y = (Xs / Ys) × B There are four basic operations for floating point arithmetic. For addition and subtraction, it is necessary to ensure that both operands have the same exponent values. This may require shifting the radix point on one of the operands to achieve alignment. Multiplication and division are straighter forward. A floating point operation may produce one of these conditions:  Exponent Overflow: A positive exponent exceeds the maximum possible exponent value.  Exponent Underflow: A negative exponent which is less than the minimum possible value.  Significand Overflow: The addition of two significands of the same sign may carry in a carry out of the most significant bit.  Significand underflow: In the process of aligning significands, digits may flow off the right end of the significand. Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 13 Computer Organization and Architecture Chapter 5 : Computer Arithmetic Floating Point Addition and Subtraction In floating point arithmetic, addition and subtraction are more complex than multiplication and division. This is because of the need for alignment. There are four phases for the algorithm for floating point addition and subtraction. 1. Check for zeros: Because addition and subtraction are identical except for a sign change, the process begins by changing the sign of the subtrahend if it is a subtraction operation. Next; if one is zero, second is result. 2. Align the Significands: Alignment may be achieved by shifting either the smaller number to the right (increasing exponent) or shifting the large number to the left (decreasing exponent). 3. Addition or subtraction of the significands: The aligned significands are then operated as required. 4. Normalization of the result: Normalization consists of shifting significand digits left until the most significant bit is nonzero. Example: Addition 110 X = 0.10001 2 100 Y = 0.101 2 Since E E , Adjust Y Y X 100 010 110 Y = 0.00101 2 2 = 0.00101 2 So, E = E = E = 110 Z X Y Now, M = M + M = 0.10001 + 0.00101 = 0.10110 Z X Y EZ 110 Hence, Z = M 2 = 0.10110 2 Z Example: Subtraction 110 X = 0.10001 2 100 Y = 0.101 2 Since E E , Adjust Y Y X 100 010 110 Y = 0.00101 2 2 = 0.00101 2 So, E = E = E = 110 Z X Y Now, M = M - M = 0.10001 - 0.00101 = 0.01100 Z X Y EZ 110 Z = M 2 = 0.01100 2 (Un-Normalized) Z 110 -001 101 Hence, Z = 0.1100 2 2 = 0.1100 2 Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 14 Computer Organization and Architecture Chapter 5 : Computer Arithmetic Start Is X == 0 Zß Y ? Stop Is Zß X Y == 0 ? Adjust X such that: E E Check E E Adjust Y such that: X Y Y X E = E = E the exponent E = E = E Z X Y Z X Y ? E = E Y X Adjust the Mantissa M = M ± M Z X Y Form the floating point number EZ Z = M 2 Z Is No ½ ≤ M 1 Post Normalize Z ? Yes Stop Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 15 Computer Organization and Architecture Chapter 5 : Computer Arithmetic Floating Point Multiplication The multiplication can be subdivided into 4 parts. 1. Check for zeroes. 2. Add the exponents. 3. Multiply mantissa. 4. Normalize the product. Example: 110 X = 0.101 2 0.1001 -010 Y = 0.1001 2 0.101 (EX + EY) As we know, Z = X Y = (M M ) 2 1001 X Y (110-010) Z = (0.101 0.1001) 2 0000 100 = 0.0101101 2 +1001 011 = 0.101101 2 (Normalized) 101101 = 0.0101101 Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 16 Computer Organization and Architecture Chapter 5 : Computer Arithmetic Floating Point Division The division algorithm can be subdivided into 5 parts 1. Check for zeroes. 2. Initial registers and evaluates the sign. 3. Align the dividend. 4. Subtract the exponent. 5. Divide the mantissa. Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 17 Computer Organization and Architecture Chapter 5 : Computer Arithmetic Example: 110 X = 0.101 2 -010 Y = 0.1001 2 (EX – EY) As we know, Z = X / Y = (M / M ) 2 X Y M / M = 0.101 / 0.1001 = (1/2 + 1/8) / (1/2 + 1/16) = 1.11 = 1.00011 X Y 0.11 2 = 0.22  0 0.22 2 = 0.44  0 0.44 2 = 0.88  0 0.88 2 = 1.76  1 0.76 2 = 1.52  1 E – E = 110 + 010 = 1000 X Y EZ 1000 1001 Now, Z = M 2 = 1.00011 2 = 0.100011 2 Z 5.5 Logical Operation Gate Level Logical Components Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 18 Computer Organization and Architecture Chapter 5 : Computer Arithmetic Composite Logic Gates Compiled By: Er. Hari Aryal haryal4gmail.com Reference: W. Stallings 19

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