Linear digital IC applications Notes

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A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS UNIT-I OP-AMP CHARACTERISTICS CREC Dept. of ECE Page 5 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS OPERATIONAL AMPLIFIER (OP-AMP): An operational amplifier is a direct-coupled high-gain amplifier usually consisting of one or more differential amplifiers and usually followed by a level translator and an output stage. An operational amplifier is available as a single integrated circuit package. The operational amplifier is a versatile device that can be used to amplify dc as well as ac input signals and was originally designed for computing such mathematical functions as addition, subtraction, multiplication, and integration. Thus the name operational amplifier stems from its original use for these mathematical operations and is abbreviated to op-amp. With the addition of suitable external feedback components, the modern day op-amp can be used for a variety of applications, such as ac and dc signal amplification, active filters, oscillators, comparators, regulators, and others. Ideal op-amp: An ideal op-amp would exhibit the following electrical characteristics: 1. Infinite voltage gain 2. Infinite input resistance so that almost any signal source can drive it and there is no loading on the preceding stage. 3. Zero output resistance Ro so that output can drive an infinite number of other devices. 4. Zero output voltage when input voltage is zero. 5. Infinite bandwidth so that any frequency signal from 0 to ∞Hz can be amplified without attenuation. 6. Infinite common mode rejection ratio so that the output common-mode noise voltage is zero. 7. Infinite slew rate so that output voltage changes occur simultaneously with input voltage changes. Equivalent circuit of an op-amp: Fig. 1.1 shows an equivalent circuit of an op-amp. V1 and V2are the two input voltage voltages. Ri is the input impedance of OPAMP. Ad Vd is an equivalent Thevenin’s voltage source and RO is the Thevenin’s equivalent impedance looking back into the terminal. This equivalent circuit is useful in analysing the basic operating principles of op-amp and in observing the effects of standard feedback arrangements. VO = Ad (V1-V2) = AdVd. CREC Dept. of ECE Page 6 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS Fig. 1.1 Equivalent circuit of OP-AMP This equation indicates that the output voltage Vo is directly proportional to the algebraic difference between the two input voltages. In other words the opamp amplifies the difference between the two input voltages. It does not amplify the input voltages themselves. The polarity of the output voltage depends on the polarity of the difference voltage Vd. Ideal Voltage Transfer Curve: Fig. 1.2 Ideal voltage transfer curve The graphic representation of the output equation is shown infig.1.2 in which the output voltage Vo is plotted against differential input voltage Vd, keeping gain Ad constant. The output voltage cannot exceed the positive and negative saturation voltages. These saturation voltages are specified for given values of supply voltages. This means that the output voltage is directly proportional to the input difference voltage only until it reaches the saturation voltages and thereafter the output voltage remains constant. Thus curve is called an ideal voltage transfer curve, ideal because output offset voltage is assumed to be zero. If the CREC Dept. of ECE Page 7 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS curve is drawn to scale, the curve would be almost vertical because of very large values of Ad. INTERNAL CIRCUIT : The operational amplifier is a direct-coupled high gain amplifier usable from 0 to over 1MHz to which feedback is added to control its overall response characteristic i.e. gain and bandwidth. The op-amp exhibits the gain down to zero frequency. The internal block diagram of an op-amp is shown in the fig 1.3. The input stage is the dual input balanced output differential amplifier. This stage generally provides most of the voltage gain of the amplifier and also establishes the input resistance of the op-amp. The intermediate stage is usually another differential amplifier, which is driven by the output of the first stage. On most amplifiers, the intermediate stage is dual input, unbalanced output. Because of direct coupling, the dc voltage at the output of the intermediate stage is well above ground potential. Therefore, the level translator (shifting) circuit is used after the intermediate stage downwards to zero volts with respect to ground. The final stage is usually a push pull complementary symmetry amplifier output stage. The output stage increases the voltage swing and raises the ground supplying capabilities of the op-amp. A well designed output stage also provides low output resistance. Fig.1.3 Block Diagram of OP-AMP Differential amplifier: Differential amplifier is a basic building block of an op-amp. The function of a differential amplifier is to amplify the difference between two input signals. The two transistors Q1 and Q2 have identical characteristics. The resistances of the circuits are equal, i.e. RE1 = R E2, RC1 = R C2 and the magnitude of +VCC is equal to the magnitude of -VEE. These voltages are measured with respect to ground. CREC Dept. of ECE Page 8 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS Fig. 1.4 Differential Amplifier To make a differential amplifier, the two circuits are connected as shown in fig. 1.4. The two +VCC and -VEE supply terminals are made common because they are same. The two emitters are also connected and the parallel combination of RE1 and RE2 is replaced by a resistance RE. The two input signals v1& v2 are applied at the base of Q1 and at the base of Q2. The output voltage is taken between two collectors. The collector resistances are equal and therefore denoted by RC = RC1 = RC2. Ideally, the output voltage is zero when the two inputs are equal. When v1 is greater then v2 the output voltage with the polarity shown appears. When v1 is less than v2, the output voltage has the opposite polarity. The differential amplifiers are of different configurations. Fig1.5. Dual input, balanced output differential amplifier.Fig.1.6. Dual input, unbalanced output differential amplifier. CREC Dept. of ECE Page 9 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS Fig.1.7.Single input, balanced output differential amplifierFig.1.8.Single input, unbalanced output differential amplifier. The four differential amplifier configurations are following: 1. Dual input, balanced output differential amplifier. 2. Dual input, unbalanced output differential amplifier. 3. Single input balanced output differential amplifier. 4. Single input unbalanced output differential amplifier. These configurations are shown in fig(1.5,1.6,1.7, 1.8), and are defined by number of input signals used and the way an output voltage is measured. If use two input signals, the configuration is said to be dual input, otherwise it is a single input configuration. On the other hand, if the output voltage is measured between two collectors, it is referred to as a balanced output because both the collectors are at the same dc potential w.r.t. ground. If the output is measured at one of the collectors w.r.t. ground, the configuration is called an unbalanced output. A multistage amplifier with a desired gain can be obtained using direct connection between successive stages of differential amplifiers. The advantage of direct coupling is that it removes the lower cut off frequency imposed by the coupling capacitors, and they are therefore, capable of amplifying dc as well as ac input signals. 1) Dual Input, Balanced Output Differential Amplifier: The circuit is shown in fig.1.10V1 and V2 are the two inputs, applied to the bases of Q1 and Q2 transistors. The output voltage is measured between the two collectors C1 and C2, which are at same dc potentials. CREC Dept. of ECE Page 10 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS D.C. Analysis: To obtain the operating point (ICQ and VCEQ) for differential amplifier dc equivalent circuit is drawn by reducing the input voltages V1 and V2 to zero as shown in fig1.9. Fig.1.9Differential Amplifier The internal resistances of the input signals are denoted by RS because RS1= RS2. Since both emitter biased sections of the different amplifier are symmetrical in all respects, therefore, the operating point for only one section need to be determined. The same values of ICQ and VCEQ can be used for second transistor Q2. Applying KVL to the base emitter loop of the transistor Q1. The value of RE sets up the emitter current in transistors Q1 and Q2 for a given value of VEE. The emitter current in Q1 and Q2 are independent of collector resistance RC. The voltage at the emitter of Q1 is approximately equal to -VBE if the voltage drop across R is negligible. Knowing the value of IC the voltage at the collector VCis given by CREC Dept. of ECE Page 11 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS Fig.1.10 Differential Amplifier VC =VCC- IC RC and VCE = VC- VE = VCC - IC RC + VBE VCE = VCC + VBE - ICRC From the two equations VCEQ and ICQ can be determined. This dc analysis is applicable for all types of differential amplifier. A.C. Analysis : The circuit is shown in fig.1.10 V1 and V2 are the two inputs, applied to the bases of Q1 and Q2 transistors. The output voltage is measured between the two collectors C1 and C2, which are at same dc potentials. Dc analysis has been done to obtain the operating point of the two transistors. To find the voltage gain Ad and the input resistance Ri of the differential amplifier, the ac equivalent circuit is drawn using r-parameters as shown infig1.11. The dc voltages are reduced to zero and the ac equivalent of CE configuration is used. Fig.1.11 Differential Amplifier A/C Analysis CREC Dept. of ECE Page 12 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS Since the two dc emitter currents are equal. Therefore, resistance r'e1 and r'e2 are also equal and designated by r'e . This voltage across each collector resistance is shown 180° out of phase with respect to the input voltages v1 and v2. This is same as in CE configuration. The polarity of the output voltage is shown in Figure. The collector C2 is assumed to be more positive with respect to collector C1 even though both are negative with respect to ground. The output voltage VO is given by Substituting ie1, & ie2 in the above expression Thus a differential amplifier amplifies the difference between two input signals. Defining the difference of input signals as Vd =V1-V2 the voltage gain of the dual input balanced output differential amplifier can be given by (E-2) Differential Input Resistance: Differential input resistance is defined as the equivalent resistance that would be measured at either input terminal with the other terminal grounded. This means that the input resistance Ri1 seen from the input signal source V1 is determined with the signal source V2 set at zero. CREC Dept. of ECE Page 13 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS Similarly, the input signal V1 set at zero to determine the input resistance Ri2 seen from the input signal source V2. Resistance RS1 and RS2 are ignored because they are very small. Substituting ie1, Similarly The factor of 2 arises because the re' of each transistor is in series. To get very high input impedance with differential amplifier is to use Darlington transistors. Another ways is to use FET. Output Resistance: Output resistance is defined as the equivalent resistance that would be measured at output terminal with respect to ground. Therefore, the output resistance RO1 measured between collector C1 and ground is equal to that of the collector resistance RC. Similarly the output resistance RO2 measured at C2 with respect to ground is equal to that of the collector resistor RC. RO1 = RO2 = RC (E-5) The current gain of the differential amplifier is undefined. Like CE amplifier the differential amplifier is a small signal amplifier. It is generally used as a voltage amplifier and not as current or power amplifier. 2) Dual Input, Unbalanced Output Differential Amplifier: Fig. 1.12 Differential Amplifier CREC Dept. of ECE Page 14 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS In this case, two input signals are given however the output is measured at only one of the two- collector w.r.t. ground as shown infig1.12. The output is referred to as an unbalanced output because the collector at which the output voltage is measured is at some finite dc potential with respect to ground. In other words, there is some dc voltage at the output terminal without any input signal applied. DC analysis is exactly same as that of first case. AC Analysis: The output voltage gain in this case is given by The voltage gain is half the gain of the dual input, balanced output differential amplifier. Since at the output there is a dc error voltage, therefore, to reduce the voltage to zero, this configuration is normally followed by a level translator circuit. Level Translator: Because of the direct coupling the dc level at the emitter rises from stages to stage. This increase in dc level tends to shift the operating point of the succeeding stages and therefore limits the output voltage swing and may even distort the output signal. To shift the output dc level to zero, level translator circuits are used. An emitter follower with voltage divider is the simplest form of level translator as shown in fig 1.13. Thus a dc voltage at the base of Q produces 0V dc at the output. It is decided by R1 and R2. Instead of voltage divider emitter follower either with diode current bias or current mirror bias as shown in fig 1.14may be used to get better results. Fig1.14 Common collector Amplifier CREC Dept. of ECE Page 15 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS In this case, level shifter, which is common collector amplifier, shifts the level by 0.7V. If this shift is not sufficient, the output may be taken at the junction of two resistors in the emitter leg. Fig.1.15 shows a complete op-amp circuit having input different amplifiers with balanced output, intermediate stage with unbalanced output, level shifter and an output amplifier. Fig.1.15 Circuit Diagram of OP-AMP OP-AMP CHARACTERISTICS DC CHARACTERISTICS: a) Input offset voltage: Input offset voltage Vio is the differential input voltage that exists between two input terminals of an op-amp without any external inputs applied. In other words, it is the amount of the input voltage that should be applied between two input terminals in order to force the output voltage to zero. Let us denote the output offset voltage due to input offset voltage Vio as Voo. The output offset voltage Voo is caused by mismatching between two input terminals. Even though all the components are integrated on the same chip, it is not possible to have two transistors in the input differential amplifier stage with exactly the same characteristics. This means that the collector currents in these two transistors are not equal, CREC Dept. of ECE Page 16 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS which causes a differential output voltage from the first stage. The output of first stage is amplified by following stages and possibly aggravated by more mismatching in them. Fig 1.16 Input offset voltage in op-amp Fig 1.17 Output offset voltage in op-amp Fig 1.18.Op-Amp with offset voltage compensating network The op-amp with offset-voltage compensating network is shown in Figure1.18. The Compensating network consists of potentiometer Ra and resistors Rb and Re. To establish a relationship between Vio, supply voltages, and the compensating components, first Thevenize the circuit, looking back into Ra from point T. The maximum Thevenin’s equivalent resistance Rmax, occurs when the wiper is at the center of the Potentiometer, as shown in Figure. Rmax =(R a /2)(R a /2) Supply voltages VCC and –VEE are equal in magnitude therefore; let us denote their magnitude by voltage V. Thus Vmax= V. CREC Dept. of ECE Page 17 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS where V2 has been expressed as a function of maximum Thevenin‘s voltage Vmax and maximum Thevenin‘s resistance, But the maximum value of V2 can be equal to Vio since V1 — V2 = Vio. Thus Equation becomes Assume Rb Rmax Rc, where Rmax = Ra/4. Using this assumption Rmax+Rb+Rc=Rb Therefore Let us now examine the effect of Vio in amplifiers with feedback. The non-inverting and inverting amplifiers with feedback are shown in Figure.1.19. To determine the effect of Vio, in each case, we have to reduce the input voltage vin to zero. Fig 1.19 Closed loop non inverting or inverting Amp With vin reduced to zero, the circuits of both non-inverting and inverting amplifiers are the sameas the circuit in Figure. The internal resistance Rin of the input signal voltage is CREC Dept. of ECE Page 18 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS negligibly small.In the figure, the non-inverting input terminal is connected to ground; therefore, assume voltageV1 at input terminal to be zero. The voltageV2 at the inverting input terminal can be determinedby applying the voltage-divider rule: b) Input offset voltage A small voltage applied to the input terminals to make the output voltage as zero when the two input terminals are grounded is called input offset voltage c) Input bias current Input bias current IB as the average value of the base currents entering into terminal of an op- amp. I =I =I B B1 B2 Obtaining the expression for the output offset voltage caused by the input bias current IB in the inverting and non-inverting amplifiers and then devise some scheme to eliminate or minimize it. CREC Dept. of ECE Page 19 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS Fig 1.20 Op-Amp In the figure, the input bias currents ‘81 and 1 are flowing into the non-inverting and inverting input leads, respectively. The non-inverting terminal is connected to ground; therefore, the voltage V1 = 0 V. The controlled voltage source A Vio =0 V since Vio= 0 V is assumed. With output resistance Ro is negligibly small, the right end of RF is essentially at ground potential; that is, resistors R1, and RF are in parallel and the bias current I, flows through them. Therefore, the voltage at the inverting terminal is d) Thermal Drift: Bias current, offset current and offset voltage change with temperature. A circuit carefully nulled at 25oc may not remain so when the temperature rises to 35oc. This is called thermal drift. AC CHARACTERISTICS: a) Slew Rate The slew rate is defined as the maximum rate of change of output voltage caused by a step input voltage. An ideal slew rate is infinite which means that op-amp’s output voltage should change instantaneously in response to input step voltage. The symbolic diagram of an OPAMP is shown in fig 1.21 Fig.1.21 Op-Amp Symbol CREC Dept. of ECE Page 20 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS b) Frequency Response Need for frequency compensation in practical op-amps: Frequency compensation is needed when large bandwidth and lower closed loop gain is desired. Compensating networks are used to control the phase shift and hence to improve the stability Frequency compensation methods: a) Dominant- pole compensation b) Pole- zero compensation. 741c is most commonly used OPAMP available in IC package. It is an 8-pin DIP chip. Parameters of OPAMP: 1. Input Offset Voltage: Fig. 1.22 Input offset voltage If no external input signal is applied to the op-amp at the inverting and non-inverting terminals the output must be zero. That is, if Vi=0, Vo=0. But as a result of the given biasing supply voltages, +Vcc and –Vcc, a finite bias current is drawn by the op-amps, and as a result of asymmetry on the differential amplifier configuration, the output will not be zero. This is known as offset. Since Vo must be zero when Vi=0 an input voltage must be applied such that the output offset is cancelled and Vo is made zero. This is known as input offset voltage. Input offset voltage (Vio) is defined as the voltage that must be applied between the two input terminals of an OPAMP to null or zero the output voltage. Fig 1.22 shows that two dc voltages are applied to input terminals to make the output zero. Vio = Vdc1- Vdc2 Vdc1 and Vdc2 are dc voltages and RS represents the source resistance. Vio is the difference of Vdc1 and Vdc2. It may be positive or negative. For a 741C OPAMP the maximum value of Vio is 6mV. It means a voltage ± 6 mV is required to one of the input to reduce the output offset voltage to zero. The smaller the input offset voltage the better the differential amplifier, because its transistors are more closely matched. CREC Dept. of ECE Page 21 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS 2. Input offset Current: Though for an ideal op-amp the input impedance is infinite, it is not so practically. So the IC draws current from the source, however smaller it may be. This is called input offset current Iio. The input offset current Iio is the difference between the currents into inverting and non-inverting terminals of a balanced amplifier as shown in fig 1.22. Iio = IB1- IB2 The Iio for the 741C is 200nA maximum. As the matching between two input terminals is improved, the difference between IB1 and IB2 becomes smaller, i.e. the Iio value decreases further. For a precision OPAMP 741C, Iio is 6 nA 3. Input Bias Current: The input bias current IB is the average of the current entering the input terminals of a balanced amplifier i.e. IB = (IB1 + IB2 ) / 2 For ideal op-amp IB=0. For 741C IB(max) = 700 nA and for precision 741C IB = ± 7 nA 4. Differential Input Resistance: (Ri) Ri is the equivalent resistance that can be measured at either the inverting or non- inverting input terminal with the other terminal grounded. For the 741C the input resistance is relatively high 2 MΩ. For some OPAMP it may be up to 1000 G ohm. 5. Input Capacitance: (Ci) Ci is the equivalent capacitance that can be measured at either the inverting and non inverting terminal with the other terminal connected to ground. A typical value of Ci is 1.4 pf for the 741C. 6. Offset Voltage Adjustment Range: 741 OPAMP have offset voltage null capability. Pins 1 and 5 are marked offset null for this purpose. It can be done by connecting 10 K ohm pot between 1 and 5. By varying the potentiometer, output offset voltage (with inputs grounded) can be reduced to zero volts. Thus the offset voltage adjustment range is the range through which the input offset voltage can be adjusted by varying 10 K pot. For the 741C the offset voltage adjustment range is ± 15 mV. 7. Input Voltage Range : Input voltage range is the range of a common mode input signal for which a differential amplifier remains linear. It is used to determine the degree of matching between the inverting and non-inverting input terminals. For the 741C, the range of the input common CREC Dept. of ECE Page 22 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS mode voltage is ± 13V maximum. This means that the common mode voltage applied at both input terminals can be as high as +13V or as low as -13V. 8. Common Mode Rejection Ratio (CMRR). CMRR is defined as the ratio of the differential voltage gain Ad to the common mode voltage gain ACM CMRR = Ad / ACM. For the 741C, CMRR is 90 dB typically. The higher the value of CMRR the better is the matching between two input terminals and the smaller is the output common mode voltage. 9. Supply voltage Rejection Ratio: (SVRR) SVRR is the ratio of the change in the input offset voltage to the corresponding change in power supply voltages. This is expressed inΔV / V or in decibels, SVRR can be defined as SVRR =ΔVio / ΔV Where ΔV is the change in the input supply voltage and ΔVio is the corresponding change in the offset voltage. For the 741C, SVRR = 150 μ V / V. For 741C, SVRR is measured for both supply magnitudes increasing or decreasing simultaneously, with R3= 10K. For same OPAMPS, SVRR is separately specified as positive SVRR and negative SVRR. 10. Large Signal Voltage Gain: Since the OPAMP amplifies difference voltage between two input terminals, the voltage gain of the amplifier is defined as Because output signal amplitude is much large than the input signal the voltage gain is commonly called large signal voltage gain. For 741C is voltage gain is 200,000 typically. 11. Output voltage Swing: The ac output compliance PP is the maximum unclipped peak to peak output voltage that an OPAMP can produce. Since the quiescent output is ideally zero, the ac output voltage can swing positive or negative. This also indicates the values of positive and negative CREC Dept. of ECE Page 23 A.MOUNIKA LECTURE NOTES ON LINEAR & DIGITAL IC APPLICATIONS saturation voltages of the OP-AMP. The output voltage never exceeds these limits for a given supply voltages +VCC and -VEE. For a 741C it is ± 13 V. 12. Output Resistance: (RO) RO is the equivalent resistance that can be measured between the output terminal of the OPAMP and the ground. It is 75 ohm for the 741C OPAMP. 13. Output Short circuit Current : In some applications, an OPAMP may drive a load resistance that is approximately zero. Even its output impedance is 75 ohm but cannot supply large currents. Since OPAMP is low power device and so its output current is limited. The 741C can supply a maximum short circuit output current of only 25mA. 14. Supply Current: IS is the current drawn by the OP-AMP from the supply. For the 741C OPAMP the supply current is 2.8 m A. 15. Power Consumption: Power consumption (PC) is the amount of quiescent power (Vin= 0V) that must be consumed by the OPAMP in order to operate properly. The amount of power consumed by the 741C is 85 m W. 16. Gain Bandwidth Product: The gain bandwidth product is the bandwidth of the OPAMP when the open loop voltage gain is reduced to 1. From open loop gain vs frequency graph At 1 MHz shown in.fig.1.24,it can be found 1 MHz for the 741C OPAMP frequency the gain reduces to 1. The mid band voltage gain is 100, 000 and cut off frequency is 10Hz. Fig.1.24 Band width of OP-AMP 17. Slew Rate: Slew rate is defined as the maximum rate of change of output voltage per unit of time under large signal conditions and is expressed in volts / μsecs. CREC Dept. of ECE Page 24

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