LECTURE NOTE ON MICROPROCESSOR

how microprocessor works and lecture notes on microprocessor and microcontroller. and lecture notes on 8085 microprocessor. how microprocessor differentiate between data and instruction. pdf free download
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Department of MCA LECTURE NOTE ON MICROPROCESSOR AND ASSEMBLY LANGUAGE PROGRAMMIMG COURSE CODE: MCA-102 Prepared by : Mrs. Sasmita Acharya Assistant Professor Department of MCA VSSUT, Burla. MODULE – 1 MICROPROCESSOR ARCHITECTURE The microprocessor is the central processing unit or cpu of a micro computer.it is the heart of the computer. INTEL 8085: It is an 8 bit Nmos microprocessor.it is an forty pin IC(integrated circuit) package fabricated on a single LSI (Large scale Integration) chip. It uses a single +5 volt d.c.(Direct Current) supply for its operation.It clock spee is 3 mhz.It consists of 3 main sections. 1-Arithmetic Logic Unit(ALU) 2-Timing and control unit 3-Several Registers Arithmetic Logic Unit: It performs various arithmetic an logical operations like aition,substraction,logical an ,xor,or,not,increment etc. Timing and control unit: It generates timing an control signals hich are necessary for the execution of the instructions.it controls the ata flo beteen cpu an peripherals. Several Registers: Registers:-it is a collection of flip flops use to store a binary word.they are used by the microprocessor for the temporary storage and manipulation of data and instructions. 8085 has the following registers: 1-8 bit accumulator i.e. register A 2-6 8 bits general purpose registers i.e. B,C,D,E,H,L 3-one 16 bit regiser i.e.stack pointer 4-16 bit Program counter,Status register,Temporary register,Instruction Register. T Th he e r re eg gi is se er r A A h ho ol ld ds s t th he e o op pe er ra an nd ds s d du ur ri in ng g p pr ro og gr ra am m e ex xe ec cu ut ti io on n.. T T Th h he e er r re e e a a ar r re e e 6 6 6 8 8 8 b b bi i it t ts s s g g ge e en n ne e er r ra a al l l p p pu u ur r rp p po o os s se e e r r re e eg g gi i is s st t te e er r rs s s B B B,,,C C C,, ,,, ,E E E,,,H H H,,,L L L a a ar r re e e t t to o o h h ha a an n nd d dl l le e e 1 1 16 6 6 b b bi i it t t d d da a at t ta a a...t t tw w wo o o 8 8 8 b b bi i it t t r re eg gi is st te er rs s c ca an n b be e c co om mb bi in ne ed d..t th hi is s i is s c ca al ll le ed d r re eg gi is st te er r p pa ai ir r..v va al li id d p pa ai ir r o of f 8 80 08 85 5 a ar re e B B-C,-E,H-L.The H-L p pa ai ir r i is s u us se ed d t to o a as s a ad dd dr re es ss s m me em mo or ry y l lo oc ca at ti io on n..B B-C,D-E E a ar re e u us se ed d f fo or r a ac cc ce es ss s a an no ot th he er r f fu un nc ct ti io on n. . BLOCK DIAGRAM OF 8085A STACK POINTER: Stack is a sequence of memory location defined by the programmer in LIFO function.That is last Element to be placed on the stack is first one is to removed .The stack pointer contain the address of the stack cup. PROGRAM COUNTER: It is the address of the next instructions to be executed. INSTRUCTION REGISTER: It holds a copy of the current instruction until it is decoded. STATUS REGISTER: It contains the status flags of 8085 microprocessor. TEMPORARY REGISTER: It is used to store intermediate results and for intermediate calculations. STATUS FLAGS: It is a set of 5 flip-flops i. Carry Flag(Cs) ii. Sign Flag(S) iii. Zero Flag(Z) iv. Parity Flag(P) v. Auxilarity carry flag(Ac) Carry Flag: It holds carry out of the resulting from the execution of an arithmetic operation. If there is a carry from addition or a borrow from substraction or comparision,the carry flag is said to 1 ortherwise it is 0. Sign Flag: It is set to 1 if the MSB of the result of an arithemetic or logical operation is 1 ortherwise it is 0. Zero Flag: It is said to 1 if the result of an arithmetic or logical operation is zero.for non zero result,it is 0. Parity Flag: It is set to 1 when the the result of the operation contains even no.of 1& it is set to 0 if there are odd no.of 1. Auxilary Carry Flag: It holds carry from bit 3 to A resulting from the execution of an arithmetic operation.If there is a carry from bit 3 to 4,the AC flag is set to 1 ortherwise it is 0. Program Status Word(PSW): It is a combination of 8-bits where five bits indicates the 5 status flags & three bits are undefined. Psw and the accumulator treated as a 16 bit unit for stack operation. BUS ORGANISATION: INTEL 8085 is a 8 bit micro processor.its data bus is 8 bit wide .8 bit of data can be transmitted in parallel form.or to the microprocessor. Address bar is 16 bit wide as memory address are of 16 bit.8 msb is the address are transmitted by on A8-A15.8 LSB is is the address are transmitted by the data bus AD0-AD7.The address or data bus transmits data & address at different moments.it can transmits data or address at a time. V AD AD ss 0- 7 V A -A CC 8 15 X1 X2 RESET IN CLK (OUT) RESET OUT HOLD IO/M HLDA S 0 INTEL S TRAP 1 8085 A RD RST 7.5 WR RST 6.5 ALE RST 5.5 SID INTR SOD INTA READY SCHEMATIC /PIN DIAGRAM OF INTEL 8085 PIN DESCRIPTION OF 8085 A -A (output)-These are address bus and are used for the most significant bits of the memory 8 15 address or 8 bits of I/O address. AD -AD (input/output)-these are time multiplexed address /data bus that is they serve dual 0 7 purpose .they are used for the least significant 8 bits of the memory address or I/O address during the first clock cycle of a machine cycle. Again they are used for data during second and third clock cycles. ALE (output)-it is an address latch enable signal. It goes high during first clock cycle of a machine cycle and enables the lower 8 bits of the address to be latched either into the memory or external latch. IO/M(output)-it is a status signal which distinguishes whether the address is for memory or I/O. when it goes high the address on the address bus is for an I/O device. When it goes low the address on the address bus is for a memory location. S , S (output)-these are status signal sent by the microprocessor to distinguish the various types 0 1 of operation Status code for Intel 8085 S S 1 0 Operations 0 0 HALT 0 1 WRITE 1 O READ 1 1 FETCH RD (output)-it is a signal to control READ operation .when it goes low the selected memory or I/O device is read. WR(output)-it is a signal to control WRITE operation .when it goes low the data on the data bus is written into the selected memory or I/O operation. READY(input)-it is used by the microprocessor to sense whether a peripheral is ready to transfer data or not .a slow peripheral may be connected to the microprocessor through READY line. if READY is high the peripheral is ready .if it is low the microprocessor waits till it goes high. HOLD (input)-it indicates that another device is requesting for the use of the address and data bus. Having received a HOLD request the microprocessor relinquishes the use of the buses as soon as the current machine cycle is completed. Internal processing may continue. the processor regains the bus after the removal of the HOLD signal. when a HOLD is acknowledged . HLDA (output)-it is a signal for HOLD acknowledgement. It indicates that the HOLD request has been received. after the removal of a HOLD request the HLDA goes low. the CPU takes over the buses half clock cycle after the HLDA goes low. INTR (input)-it is an interrupt request signal. Among interrupts it has the lowest priority. An interrupt is used by io devices to transfer data to the microprocessor without wasting its time. INTA (output)-it is an interrupt acknowledgement sent by the microprocessor after INTR is received. RST5.5, RST6.5, RST 7.5(input)-these are interrupts. Signals are the restart interrupt, they causes an internal restart to be automatically inserted each of them of a programmable mask. TRAP-TRAP has the highest priority. It is used in emergency situation. it is an non-mask able interrupt. Order of priority- TRAP RST 7.5 RST 6.5 RST 5.5 INTR When an interrupt is recognize the next instruction is executed from a fixed location in memory. A subroutine is executed which is called ISS(interrupt service subroutine). INTERRUPTS ISS ADDRESS TRAP 0024 RST 5.5 002C RST 6.5 0034 RST 7.5 003C RESET IN (input)-it resets the program counter to zero .it also resets interrupts enable that is an HLDA flip-flops. RESETOUT (output)-it indicates that the CPU is being reset. X1, X2 (input)-these are terminals to be connected to an external crystal oscillator which drives an internal circuitry of the microprocessor to produce a suitable clock for the operation of microprocessor. CLK (output)-it is a clock output for user, which can be used for other digital integrated circuits. th SID (input)-it is data line for serial input. The data on this line is loaded into the 7 bit of the accumulator when rim (read interrupt mask) instruction is executed. th SOD (output)- it is data line for serial output. The 7 bit of the accumulator is output on sod line when sim instruction is executed. Vcc-it is +5 volt dc supply. Vss-it is the ground reference. INSTRUCTION AND DATA FORMATS Intel 8085 is an 8-bit microprocessor. It handles 8-bit data at a time. One byte consists of 8- bits.A memory location for Intel 8085 microprocessor is designed to accumulate 8-bit data. If 16- bit data are to be stored, they are stored in consecutive memory locations. The address of memory location is 0f 16-bit i.e. 2 bytes. The various techniques to specify data for instructions are: (1) 8-bit or 16-bit data may be directly given in the instruction itself. (2) The address of the memory location, I/O port or I/O device, where data resides, may be given in the instruction itself. (3)In some instructions only one register is specified. The content of the specified register is one of the operand and other operand is the accumulator. (4) Some instructions specify two registers. The contents of the registers are the required data. Due to different ways of specifying data for instruction are not of same length. So there are three types of instructions of Intel 8085: (1)Single byte instruction (2)2-byte instruction (3)3-byte instruction Single-Byte instruction. The content information regarding operands in the opcode itself .These are of one byte. Ex-MOV A,B ; Move the content of register B to A 78H is opcode for MOV A,B. The binary form of opcode 78H is 01111000. The first two bit i.e. 01 for MOV operation; the next 3 bits i.e. 111 for register A and last 3 bits 000 are for register B. Two-Byte instruction. st nd In case of two byte instruction the 1 byte of the instruction is opcode and 2 byte is either data or address. Both bytes are stored in two consecutive memory locations. Ex-MVI B,05; Move 05 to register B 06,05; MVI B,05 in the code form st nd Here in this case the 1 byte i.e. 06 is the opcode for MVI B and 2 byte i.e. 05 is the data which is to be moved to register B. Three-Byte instruction. st nd rd In case of three bytes instruction the 1 byte of instruction is opcode and 2 and 3 byte of instruction are either 16-bit data or 16-bit address. They are stored in three consecutive memory locations. Ex-LXI H, 2400H ; load H-L pair with 2400H 21,00,24; LXI H, 2400H in code form. st nd Here 1 byte i.e. 21 is the opcode for instruction LXI H. The 2 byte i.e. 00 is 8 LSBs of data rd which is loaded in to register L. The 3 byte i.e. 24 is 8 MSBs of data which is loaded in to register H. ADDRESSING MODES OF 8085 : Addressing mode: These are various technique to specify data for instruction a) Direct addressing mode b) Register addressing mode c) Register addressing mode d) Immediate addressing mode e) Implicit addressing mode. a) Direct addressing mode: In this addressing mode the address of the operand is given in the instruction. Ex: STA 2000H IN 02H b) Register addressing mode: In this addressing mode the operands are in the general purpose register. The opcode specify the address of the register and the operation to be Perform. Ex: MOV A,B ADD B c) Register indirect addressing mode: i. In this addressing mode the address of the operand is specify by a register pair. Ex: LXI H,2000H MOV A,M d) Immediate addressing mode: i. In this adressing mode operand is specify with in the instruction. ii. Ex: MVI A,05H // Move immediate data 05H to Accumulator. e) Implicit addressing mode: I. This instruction operates on the content of the accumulator. II. They don’t required operand address. III. EX: CMA //Complement DATA TRANSFER GROUP 1. MOV r1,r2 (Move data; move the content of one register to another) r1r2. State :none. addressing:register addressing. machine cycle:1. The content of resister r2 is move to register is moved to register 1.For example,the instruction MOV A,B moves the contents of resister b to register A.The instruction MOV B,A moves the content of register A to register B.The time for the execution of this instruction is 4 clock period.One clock period is called is state.No lag is affected. 2. MOV r,M (move the content of memory to register) rH-L. State:7.flag:none. Addressing:register indirect. Machine cycle:2 The content of memory location,whose address is in H-L pair is moved to register r. Example LXI H,2000H load H-L pair by 2000H MOV B,M Move the content of the memory location 2000H to register B. HLT Halt In this example the instruction LXI H,2000H loads H-L pair with 2000Hwhich is the address of a memory loation.Then the instruction MOV B,M will move the content of memory location 2000H to register B. 3. MOV M,r. (Move the content of register to to memory) H-Lr. States:7. Flag:none. Addressing:register indirect. Machine cycle:2 The content of register r is moved to the memory location address by H-L pair.For example,MOV M,C moves the content of register c to the memory location whose address is in H-L pair. 4. MVI r,data.(moves immediate data to register) rdata. States:7. Flag:none.adressing:immediate.machine cycle :2 st nd The 1 byte of the instruction is its opcode.the 2 byte of the instruction is the data which is moved to register r.For example ,the MVI A,05 moves 05 to register A.In the code form it is written as 3E,05.The opcode for MVI A is 3E,05.The opcode for MVI A is 3E and 05 is the data which is to be moved to register A. 5. MVI M,data (Move immediate data to memory) H-Ldata . states:10.flags:none addressing:immediate/reg. Indirect. Machine cycle:3. The data is moved to the memory location whose address is in H-L pair. Example LXI H,2400H Load H-L pair with 2400H. MVI M,08 Move 08 to the memory location 2400H. HLT Halt. In the above example the instruction LXI H,2400H Loads H-L pair with 2400H which is the address of a memory location.Then the instruction MVI M,08 will move 08 to memory location 2400H.In the code form it is written as 36,08.The opcode for MVI M is 36 and 08 is the data which is to be moved to the memory location 2400H. 6. LXI rp, 16-bit data (load register pair immediate) rpdata 16 bits, rh8 MSBs, rl8LSBs of data States: 10, Flags: none, Addressing: Immediate, Machine Cycles: 3 This instruction loads 16 bit immediate data into register pair rp. This instruction is for register pair; only high order register is mentioned after the instruction. For example; H in the LXI H stands for H-L pair. Similarly, LXI B is for B-C pair. LXI H, 2500H loads 2500H into H-L pair. H with 2500H denotes that the data 2500 is in hexadecimal. In the code form it is written as st 21,00,25. The 1 byte of the instruction 21 is the opcode for LXI H. The second byte 00 is of 8LSBs of the memory address and it is loaded inyo register L. The third byte 25 is 8 MSBS of the data and it is loaded into register H 7. LDA addr (Load accumulator direct) Aaddr States :13, flags :none,Addressing:Direct,Machine cycle:4 nd rd The content of memory location , whose address is specified by the 2 and 3 bytes of the instruction; is loaded into the accumulator.The instruction LDA 2400H will load the content of the memory location 2400H into the accumulator .Inthe code form it is written as 3A,00,24.The st nd 1 byte 3A is the opcode of the instruction . The 2 byte 00 is of 8LSBs of the memory rd address.The 3 byte 24 is 8Msbs of the memory address. 8. STA addr (store accumulator direct) addrA.States:13.Flags:none.Addressing:direct.Machine cycle:4. The content of the accumulator is stored in the memory location whose address is specified by nd rd tthe 2 and 3 byteof the instruction.STA 2000H will store the content of the accumulator in the memory location 2000H. 9. LHLD addr (load H-L pair direct). Laddr,Haddr+1.States:16.Flags:none.Addressing:direct.Machine cycle:5 nd rd The content of the memory location ,whose address is specified by 2 and 3 bytes of the instruction,is loaded into rsister L.The content of the next memory location is loaded into resister H. For example ,LHLD 2500H will load the content of the memory location 2500H into register L. The content of the memory location 2501H is loaded into register H. 10. SHLD addr (store H-L pair direct) addrL,addr+1H.States:16,Flags:none,Addressing:direct.Machine cycles:5 The content of the register L is stored in the memory location whose address is specified by the nd rd 2 and 3 bytes of the instruction.The content of register H is stored in the next memory location .For example ,SHLD 2500H will stored the content of register L in the memory location 2500H.The content of the register H is stored in the memory location2501H. 11. LDAX rp (LOAD accumulator indirect) Arp.states:7,Flags:none,Addressing:register indirect,Machine cycle:2 The content of the memory location ,whose address is in the register pair rp,is loaded into the accumulator.For example ,LDAX B will load the content of the memory location,whose address is in B-C pair,into the accumulator.Th instruction is used only for B-C and D-E register pairs. 12. STAX rp (store accumulator indirect) rpA.States:7.Flags:none.Addressing :register indirect.Machine cycles:2. The content of the accumulator is stored in the memory location whose address is in the register pair rp.For example ,STAX D will stored the content of the accumulator in the memory location whose address is in D-E pair.This instruction is true only for register pair B-C and D-E. 13. XCHG (Exchange the content of the H-L with D-E pair) H-LD-E.States:4,Flags:none,Addressing :register,Machine cycle:1. The content of H-L pair are exchanged with contents of D-E pair ARITHMETIC GROUP The Instruction of this group performs arithmetic operation such as Addition, Subtraction, Increment or Decrement of the content of the register or memory. 1. Add r (Add register to accumulator) A ← A + r The content of register r is added to the content of the accumulator,and the sum is placed in the accumulator. 2. ADD M( Add memory to accumulator) A ← A + H-L The content of the memory location addressed by H-L pair is added to the content to the accumulator. The sum is placed in the accumulator. 3. ADC r (Add register with carry to accumulator) A ← A + r + CS The content of register r and carry status are added to the content of the accumulator. The sum is placed in the accumulator. 4. ADC M (Add memory with carry to accumulator) A ← A + H-L + CS The content of the memory location addressed by H-L pair add carry status are added to the content of the accumulator. The sum is placed in the accumulator. 5. ADI data (Add immediate data to accumulator) A ← A + data st The immediate data is added to the content to the accumulator. The 1 byte of the instruction is nd its opcode. The 2 byte of the instruction is data and it is added to the content of the accumulator. The sum is placed in the accumulator. FOR EXAMPLE: The instruction ADI 08 will add 08 to the content of the accumulator and placed the result in the accumulator. In code form the instruction is written as C6 08. accumulator. BRANCH CONTROL GROUP The instruction of this group change the normal sequence of the program. There are of two types of branch instruction • Conditional branch instruction • Unconditional branch instruction Conditional branch instruction:- It transfer the program to the specified level when certain condition is satisfied. Unconditional branch instruction:- It transfer the program to the specified level unconditionally. Example:-JMP addr(label). Conditional Jump addr(label): 1. JZ addr(label):-Jump if the result is zero,Z=1. 2. JNZ addr(label):-jump if the result is not zero,Z=0. 3. JCaddr(label):-jump if there is a carry,CS=1. 4. JNC addr(label):-jump if there is no carry,CS=0. 5. JP addr(label):-jump if the result is plus,S=0. 6. JM addr(label):-jump if the result is minus,S=1. 7. JPE addr(label):-jump if even parity,P=1. 8. JPO addr(label):-jump if odd parity,P=0. CALL addr(label):- • Used in unconditional branch instruction. • Used to call a sub-routine,before control its transfer to the subroutine . • The content of program counter is saved in the stack. • Call is 3-byte instruction. Conditional CALL addr(label): 1. CC addr(label):-call subroutine if carry status CS=1. 2. CNC addr(label):-call subroutine if carry status CS=0. 3. CZ addr(label):-call subroutine if the result is zero ;the zero status Z=1. 4. CNZ addr(label):-call subroutineif the result is not zero;the zero status Z=0. 5. CP addr(label):-call subroutineif the result is plus;the sign status S=0. 6. CM addr(label):-call subroutineif the result is minus;the sign status S=1. 7. CPE addr(label):-call subroutine if even parity;the parity status P=1. 8. CPO addr(label):-call subroutine if odd parity;the parity status P=0. RET(Return sub routine):- • It is used at the end of a subroutine. • Before the execution of a subroutine the address of the next instruction of the main program is saved in the stack. • The content of the stack pointer is incremented by 2 to indicate the new stack top. Conditional Return:- 1. RC:-Return from subroutine if carry status CS=1. 2. RNC:-Return from subroutine if carry status CS=0. 3. RZ:-Return from subroutine if the result is zero;the zero status Z=1. 4. RNZ:-Return from subroutineif the result is not zero;the zero status Z=0. 5. RP:-Return from subroutineif the result isplus;the sign statusS=0. 6. RM:-:-Return from subroutine if the result is minus ,the sign status S=1. 7. RPE:-:-Return from subroutine if even parity,the parity status P=1. 8. RPO:-_:-Return from subroutine if odd parity,the parity status P=0. RST n (restart) Instruction:- • It is a one-word call instruction the content of a program counter is saved in the stack,the program jumps to the instruction ,starting at restart location. • The address of the restart location is 8 times n. There are 8 RST restart instruction carrying from RST0-RST7. • These are software interrupts used by the programmer to interrupt the microprocessor. • The restart instruction and location are as follows:- Instruction Opcode Restart Location RST0 C7 0000 RST1 CF 0008 RST2D7 0010 RST3 DF 0018 RST4 E7 0020 RST5 EF 0028 RST6 F7 0030 RST7FF 0038 PCHL instruction:- • Jump to address specified by H-Lpair. • The content of H-Lpairare transferred to the program counter. • The content of register L will be loaded to 8 LSBs of PC and content of register H will loaded to 8 MSBs. EXAMPLES OF ASSEMBLY LANGUAGE PROGRAMS 1. ALP FOR ADDITION OF TWO 8-BIT NUMBERS; SUM 8-BIT Mnemonics Operand Comments st LXI H, 2501 H Get Address of 1 No. in H-L pair st MOV A, M 1 no. in accumulator INX H Increment content of H-L pair st nd ADD M Add 1 no. and 2 no. STA 2503 H Store sum in 2503 H. HLT Stop the program. DATA 2501- 49 H 2502- 56 H The sum is stored in memory location 2503 H. RESULT 2503- 9F H. 2. ALP FOR SUBTRACTION OF TWO 8-BIT NUMBERS Mnemonics Operand Comments st LXI H, 2501 H Get address of 1 no. in H-L pair. st MOV A, M 1 no. in accumulator. INX H Content of H-L pair in 2502 H. st nd SUB M 1 no. – 2 no. INX H Content of H-L pair becomes 2503 H. MOV M, A Store results in 2503 H. HLT Stop the program. DATA 2501- 49 H 2502- 32 H The result is stored in memory location 2503 H. RESULT 2503- 17 H. 3. ALP FOR ADDITION OF TWO 8-BIT NUMBERS; SUM:16-BITS Labels Mnemonics Operand Comment st LXI H, 2501 H Address of 1 no. in H-L pair. MVI C, 00 MSBs of sum in register C. Initial value = 00. st MOV A, M 1 no. in accumulator. nd INX H Address of 2 no. 2502 in H-L pair. st nd ADD M 1 no. + 2 no. JNC AHEAD Is carry? No, go to the label AHEAD. INR C Yes, increment C. AHEAD: STA 2503 H LSBs of sum in 2503 H. MOV A , C MSBs of sum in accumulator. STA 2504 H MSBs of sum in 2504 H. HLT Stop the program. DATA 2501- 98 H 2502- 9A H RESULT 2503- 32 H, LSBs of sum. 2504- 01 H, MSBs of sum. 4. ALP FOR DECIMAL ADDITION OF TWO 8-BIT NUMBERS; SUM:16-BITS Labels Mnemonics Operand Comment st LXI H, 2501 H Address of 1 no. in H-L pair. MVI C, 00 MSDs of sum in register C. Initial value = 00. st MOV A, M 1 no. in accumulator. nd INX H Address of 2 no. 2502 in H-L pair. st nd ADD M 1 no. + 2 no. DAA Decimal adjust. JNC AHEAD Is carry? No, go to the label AHEAD. INR C Yes , increment C. AHEAD: STA 2503 H LSDs of sum in 2503 H.

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