Single cycle mips processor verilog code

single cycle processor design in verilog and single cycle processor in computer architecture
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Dr.ShaneMatts,United States,Teacher
Published Date:23-07-2017
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1 Single-Cycle Processors: Datapath & Control Arvind Computer Science & Artificial Intelligence Lab M.I.T. Based on the material prepared by Arvind and Krste Asanovic 6.823 L5- 2 Arvind Instruction Set Architecture (ISA) versus Implementation • ISA is the hardware/software interface – Defines set of programmer visible state – Defines instruction format (bit encoding) and instruction semantics –Examples: MIPS, x86, IBM 360, JVM • Many possible implementations of one ISA – 360 implementations: model 30 (c. 1964), z900 (c. 2001) –x86 implementations: 8086 (c. 1978), 80186, 286, 386, 486, Pentium, Pentium Pro, Pentium-4 (c. 2000), AMD Athlon, Transmeta Crusoe, SoftPC – MIPS implementations: R2000, R4000, R10000, ... –JVM: HotSpot, PicoJava, ARM Jazelle, ... September 26, 2005 6.823 L5- 3 Arvind Processor Performance Time = Instructions Cycles Time Program Program Instruction Cycle – Instructions per program depends on source code, compiler technology, and ISA – Cycles per instructions (CPI) depends upon the ISA and the microarchitecture – Time per cycle depends upon the microarchitecture and the base technology Microarchitecture CPI cycle time Microcoded 1 short this lecture Single-cycle unpipelined 1 long Pipelined 1 short September 26, 2005 6.823 L5- 4 Arvind Microarchitecture: Implementation of an ISA control Controller status points lines Data path Structure: How components are connected. Static Behavior: How data moves between components Dynamic September 26, 2005 Hardware Elements • Combinational circuits OpSelect - Add, Sub, ... – Mux, Demux, Decoder, ALU, ... - And, Or, Xor, Not, ... - GT, LT, EQ, Zero, ... Sel Sel lg(n) lg(n) O O 0 A A 0 0 O O 1 1 Result A O A . A 1 . . . ALU . Mux . . lg(n) . Comp? . O B O n-1 A n­ n-1 1 • Synchronous state elements – Flipflop, Register, Register file, SRAM, DRAM register D Clk ... D D D D 0 1 2 n-1 En En En ff ... ff ff ff ff Clk Clk D ... Q Q Q Q Q Q 0 1 2 n-1 Edge-triggered: Data is sampled at the rising edge September 26, 2005 Demux Decoder… … … … 6.823 L5- 6 Arvind Register Files Clock WE we rs1 rd1 ReadSel1 ReadData1 Register rs2 ReadSel2 rd2 ReadData2 file WriteSel ws 2R+1W wd WriteData rs1 ws clk wd 32 5 5 register 0 rd1 32 32 register 1 we rs2 5 32 register 31 rd2 32 32 • No timing issues in reading a selected register • Register files with a large number of ports are difficult to design – Intel’s Itanium, GPR File has 128 registers with 8 read ports and 4 write ports September 26, 2005 6.823 L5- 7 Arvind A Simple Memory Model WriteEnable Clock Address MAGIC ReadData RAM WriteData Reads and writes are always completed in one cycle • a Read can be done any time (i.e. combinational) • a Write is performed at the rising clock edge if it is enabled ⇒ the write address and data must be stable at the clock edge Later in the course we will present a more realistic model of memory September 26, 2005 6.823 L5- 8 Arvind Implementing MIPS: Single-cycle per instruction datapath & control logic September 26, 2005 6.823 L5- 9 Arvind The MIPS ISA Processor State 32 32-bit GPRs, R0 always contains a 0 32 single precision FPRs, may also be viewed as 16 double precision FPRs FP status register, used for FP compares & exceptions PC, the program counter some other special registers Data types 8-bit byte, 16-bit half word 32-bit word for integers 32-bit word for single precision floating point 64-bit word for double precision floating point Load/Store style instruction set data addressing modes- immediate & indexed branch addressing modes- PC relative & register indirect Byte addressable memory- big endian mode All instructions are 32 bits September 26, 2005 6.823 L5- 10 Arvind Instruction Execution Execution of an instruction involves 1. instruction fetch 2. decode and register fetch 3. ALU operation 4. memory operation (optional) 5. write back and the computation of the address of the next instruction September 26, 2005 6.823 L5- 11 Arvind Datapath: Reg-Reg ALU Instructions RegWrite 0x4 clk Add inst25:21 we inst20:16 rs1 rs2 addr PC inst15:11 rd1 inst ALU ws z wd rd2 Inst. clk GPRs Memory ALU inst5:0 Control OpCode RegWrite Timing? 6 5 5 5 5 6 0 rs rt rd 0 func rd ← (rs) func (rt) 31 26 25 21 20 16 15 11 5 0 September 26, 2005 6.823 L5- 12 Arvind Datapath: Reg-Imm ALU Instructions RegWrite 0x4 clk Add we inst25:21 rs1 rs2 addr rd1 PC inst20:16 inst ws ALU wd rd2 z Inst. clk GPRs Memory inst15:0 Imm Ext inst31:26 ALU Control ExtSel OpCode 655 16 opcode rs rt immediate rt ← (rs) op immediate 31 26 25 2120 16 15 0 September 26, 2005 6.823 L5- 13 Arvind Conflicts in Merging Datapath RegWrite Introduce 0x4 clk Add muxes we inst25:21 rs1 rs2 addr rd1 PC inst20:16 inst ws ALU inst15:11 wd rd2 z Inst. clk GPRs Memory inst15:0 Imm Ext inst31:26 ALU inst5:0 Control ExtSel OpCode 6 5 5 5 5 6 0 rs rt rd 0 func rd ← (rs) func (rt) opcode rs rt immediate rt ← (rs) op immediate September 26, 2005 6.823 L5- 14 Arvind Datapath for ALU Instructions RegWrite 0x4 clk Add we 25:21 rs1 20:16 rs2 addr rd1 PC inst ws ALU wd rd2 z 15:11 Inst. clk GPRs Memory 15:0 Imm Ext 31:26, 5:0 ALU Control ExtSel OpSel BSrc RegDst OpCode Reg / Imm rt / rd 6 5 5 5 5 6 0 rs rt rd 0 func rd ← (rs) func (rt) opcode rs rt immediate rt ← (rs) op immediate September 26, 2005 6.823 L5- 15 Arvind Datapath for Memory Instructions Should program and data memory be separate? Harvard style: separate (Aiken and Mark 1 influence) - read-only program memory - read/write data memory at some level the two memories have to be the same Princeton style: the same (von Neumann’s influence) - A Load or Store instruction requires accessing the memory more than once during its execution September 26, 2005 6.823 L5- 16 Arvind Load/Store Instructions:Harvard Datapath RegWrite MemWrite WBSrc 0x4 clk ALU / Mem Add we “base” clk rs1 rs2 we rd1 addr PC ws addr inst ALU wd rd2 z GPRs rdata Inst. clk Data Memory disp Imm Memory Ext wdata ALU Control OpCode RegDst ExtSel OpSel BSrc 6 5 5 16 addressing mode opcode rs rt displacement (rs) + displacement 31 26 25 21 20 16 15 0 rs is the base register rt is the destination of a Load or the source for a Store September 26, 2005 6.823 L5- 17 Arvind MIPS Control Instructions Conditional (on GPR) PC-relative branch 6 5 5 16 opcode rs offset BEQZ, BNEZ Unconditional register-indirect jumps 6 5 5 16 opcode rs JR, JALR Unconditional absolute jumps 6 26 opcode target J, JAL • PC-relative branches add offset×4 to PC+4 to calculate the target address (offset is in words): ±128 KB range • Absolute jumps append target×4 to PC31:28 to calculate the target address: 256 MB range • jump-&-link stores PC+4 into the link register (R31) • All Control Transfers are delayed by 1 instruction we will worry about the branch delay slot later September 26, 2005 6.823 L5- 18 Arvind Conditional Branches (BEQZ, BNEZ) PCSrc RegWrite MemWrite WBSrc br pc+4 0x4 Add Add clk we clk rs1 rs2 addr we PC rd1 inst ws addr ALU wd rd2 Inst. clk z GPRs rdata Data Memory Imm Memory Ext wdata ALU Control zero? OpCode RegDst ExtSel OpSel BSrc September 26, 2005 6.823 L5- 19 Arvind Register-Indirect Jumps (JR) PCSrc RegWrite MemWrite WBSrc br rind pc+4 0x4 Add Add clk we clk rs1 rs2 addr we PC rd1 inst ws addr ALU wd rd2 Inst. clk z GPRs rdata Data Memory Imm Memory Ext wdata ALU Control zero? OpCode RegDst ExtSel OpSel BSrc September 26, 2005 6.823 L5- 20 Arvind Register-Indirect Jump-&-Link (JALR) PCSrc RegWrite MemWrite WBSrc br rind pc+4 0x4 Add Add clk we clk rs1 rs2 addr 31 we PC rd1 inst ws addr ALU wd rd2 Inst. clk z GPRs rdata Data Memory Imm Memory Ext wdata ALU Control zero? OpCode RegDst ExtSel OpSel BSrc September 26, 2005

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