Arithmetic circuits ppt

arithmetic circuits in digital electronics ppt and combinational arithmetic logic circuits ppt
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Dr.ShawnPitt,Netherlands,Teacher
Published Date:25-07-2017
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Arithmetic Circuits-2 • Multipliers – Array multipliers • Shifters – Barrel shifter – Logarithmic shifter James Morizio ECE 261 1Binary Multiplication M-1 N-1 i i Y = Σ Y 2 X = Σ X 2 i i i=0 i=0 Multiplier Multiplicand Product Z = X Y N-1 M-1 i+j = Σ (Σ X Y 2 ) i j i=0 j=0 Partial products • Product = Sum of partial products James Morizio ECE 261 2Multiplication 1100 : 12 10 0101 : 5 • Example: 10 James Morizio ECE 261 3Multiplication 1100 : 12 10 0101 : 5 • Example: 10 1100 James Morizio ECE 261 4Multiplication 1100 : 12 10 0101 : 5 • Example: 10 1100 0000 James Morizio ECE 261 5Multiplication 1100 : 12 10 0101 : 5 • Example: 10 1100 0000 1100 James Morizio ECE 261 6Multiplication 1100 : 12 10 0101 : 5 • Example: 10 1100 0000 1100 0000 James Morizio ECE 261 7Multiplication 1100 : 12 10 0101 : 5 • Example: 10 1100 0000 1100 0000 00111100 : 60 10 James Morizio ECE 261 8Multiplication multiplicand 1100 : 12 10 0101 : 5 multiplier • Example: 10 1100 partial 0000 products 1100 0000 00111100 : 60 product 10 • M x N-bit multiplication – Produce N M-bit partial products – Sum these to produce M+N-bit product James Morizio ECE 261 9The Binary Multiplication 1 0 1 0 1 0 Multiplicand 1 0 1 1 Multiplier AND operation 1 0 1 0 1 0 1 0 1 0 1 0 Partial Products 0 0 0 0 0 0 + 1 0 1 0 1 0 1 1 1 0 0 1 1 1 0 James Morizio ECE 261 10General Form • Multiplicand: Y = (y , y , …, y , y ) M-1 M-2 1 0 • Multiplier: X = (x , x , …, x , x ) N-1 N-2 1 0 M−1 N−1 N−1M−1     j i i+j P= y 2 x 2 = x y 2   ∑ ∑ ∑∑ j i i j   • Product: j=0  i=0  i=0 j=0   multiplicand y y y y y y 5 4 3 2 1 0 x x x x x x multiplier 5 4 3 2 1 0 x y x y x y x y x y x y 0 5 0 4 0 3 0 2 0 1 0 0 x y x y x y x y x y x y 1 5 1 4 1 3 1 2 1 1 1 0 x y x y x y x y x y x y partial 2 5 2 4 2 3 2 2 2 1 2 0 products x y x y x y x y x y x y 3 5 3 4 3 3 3 2 3 1 3 0 x y x y x y x y x y x y 4 5 4 4 4 3 4 2 4 1 4 0 x y x y x y x y x y x y 5 5 5 4 5 3 5 2 5 1 5 0 product p p p p p p p p p p p p 11 10 9 8 7 6 5 4 3 2 1 0 James Morizio ECE 261 11multiplier x Dot Diagram • Each dot represents a bit x 0 partial products x 15 James Morizio ECE 261 12The Array Multiplier x x x x 3 2 1 0 y 0 x x x x 3 2 1 0 Z 0 y 1 HA FA FA HA Z 1 x x x x y 3 2 1 0 2 FA FA FA HA FA: Full adder Z 2 x x x x y 3 2 1 0 3 HA: Half adder (two inputs) FA FA FA HA Propagation delay = ? Z Z Z Z Z 7 6 5 4 3 James Morizio ECE 261 13The MxN Array Multiplier — Critical Path HA FA FA HA Critical Path 1 FA FA FA HA Critical Path 2 Critical Path 1 & 2 FA FA FA HA James Morizio ECE 261 14Carry-Save Multiplier HA HA HA HA HA FA FA FA Carries saved for next HA FA FA FA adder stage Unique critical path HA FA FA HA Trade offs? James Morizio ECE 261 15Adder Cells in Array Multiplier P V DD V DD A C i P S A A P C i A B B P V DD V DD P A P C o C C i i C i A P Identical Delays for Carry and Sum James Morizio ECE 261 16Multiplier Floorplan X X X X 3 2 1 0 Y 0 HA Multiplier Cell Y 1 C S C S C S C S Z 0 FA Multiplier Cell Y 2 C S C S C S C S Vector Merging Cell Z 1 Y 3 X and Y signals are broadcasted C S C S C S C S Z through the complete array. 2 C C C C S S S S Z Z Z Z Z 7 6 5 4 3 James Morizio ECE 261 17Multipliers —Summary • Optimiz ation Goals Diffe re nt Vs Binary Adde r • Onc e Again: Ide ntify Critic al P ath • Othe r pos s ible te c hnique s (Wallace tree - Logarithmic ve rs us Line ar multiplier) - Data e nc oding (Booth) - P ipe lining James Morizio ECE 261 18Comparators • 0’s detector: A = 00…000 • 1’s detector: A = 11…111 • Equality comparator: A = B • Magnitude comparator: A B James Morizio ECE 261 191’s & 0’s Detectors • 1’s detector: N-input AND gate • 0’s detector: NOTs + 1’s detector (N-input NOR) A 7 A 6 A 3 A A 5 2 A allzeros 4 allones A 1 A 3 A A 0 2 A 1 A 0 A 7 A 6 A 5 A 4 A allones 3 A 2 A 1 A 0 James Morizio ECE 261 20

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