Introduction to virtual machines ppt

virtual machine migration techniques ppt and virtual machine ppt presentation
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Published Date:23-07-2017
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Joel Emer December 12, 2005 6.823, L25-1 Virtual Machines and Dynamic Translation: Implementing ISAs in Software Joel Emer Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology Based on the material prepared by Krste Asanovic and Arvind Joel Emer December 12, 2005 6.823, L25-2 Software Applications How is a software application encoded? – What are you getting when you buy a software application? – What machines will it work on? – Who do you blame if it doesn’t work, » i.e., what contract(s) were violated? Joel Emer December 12, 2005 6.823, L25-3 ISA + Environment = Virtual Machine ISA alone not sufficient to write useful programs, need I/O • Direct access to memory mapped I/O via load/store instructions problematic – time-shared systems – portability • Operating system responsible for I/O – sharing devices and managing security – hiding different types of hardware (e.g., EIDE vs. SCSI disks) • ISA communicates with operating system through some standard mechanism, i.e., syscall instructions – example convention to open file: addi r1, r0, 27 27 is code for file open addu r2, r0, rfname r2 points to filename string syscall cause trap into OS On return from syscall, r1 holds file descriptor Joel Emer December 12, 2005 6.823, L25-4 Application Binary Interface (ABI) • Programs are usually distributed in a binary format that encodes the program text (instructions) and initial values of some data segments (ABI) • Virtual machine specifications include – which instructions are available (the ISA) – what system calls are possible (I/O, or the environment) – what state is available at process creation • Operating system implements the virtual machine – at process startup, OS reads the binary program, creates an environment for it, then begins to execute the code, handling traps for I/O calls, emulation, etc. Joel Emer December 12, 2005 6.823, L25-5 OS Can Support Multiple VMs • Virtual machine features change over time with new versions of operating system – new ISA instructions added – new types of I/O are added (e.g., asynchronous file I/O) • Common to provide backwards compatibility so old binaries run on new OS – SunOS 5 (System V Release 4 Unix, Solaris) can run binaries compiled for SunOS4 (BSD-style Unix) – Windows 98 runs MS-DOS programs – Solaris 10 runs Linux binaries • If ABI needs instructions not supported by native hardware, OS can provide in software Joel Emer December 12, 2005 6.823, L25-6 Supporting Multiple OSs on Same Hardware • Can virtualize the environment that an operating system sees, an OS-level VM • Hypervisor layer implements sharing of real hardware resources by multiple OS VMs that each think they have a complete copy of the machine – Popular in early days to allow mainframe to be shared by multiple groups developing OS code (VM/360) – Used in modern mainframes to allow multiple versions of OS to be running simultaneously Î OS upgrades with no downtime – Example for PCs: VMware allows Windows OS to run on top of Linux (or vice-versa) • Requires trap on access to privileged hardware state – easier if OS interface to hardware well defined Joel Emer December 12, 2005 6.823, L25-7 ISA Implementations Partly in Software Often good idea to implement part of ISA in software: • Expensive but rarely used instructions can cause trap to OS emulation routine: – e.g., decimal arithmetic in µVax implementation of VAX ISA • Infrequent but difficult operand values can cause trap – e.g., IEEE floating-point denormals cause traps in almost all floating-point unit implementations • Old machine can trap unused opcodes, allows binaries for new ISA to run on old hardware – e.g., Sun SPARC v8 added integer multiply instructions, older v7 CPUs trap and emulate Joel Emer December 12, 2005 6.823, L25-8 Supporting Non-Native ISAs Run programs for one ISA on hardware with different ISA • Emulation (OS software interprets instructions at run-time) – E.g., OS for PowerPC Macs had emulator for 68000 code • Binary Translation (convert at install and/or load time) – IBM AS/400 to modified PowerPC cores – DEC tools for VAX-Alpha and MIPS-Alpha • Dynamic Translation (non-native ISA to native ISA at run time) – Sun’s HotSpot Java JIT (just-in-time) compiler – Transmeta Crusoe, x86-VLIW code morphing • Run-time Hardware Emulation – IBM 360 had IBM 1401 emulator in microcode – Intel Itanium converts x86 to native VLIW (two software-visible ISAs) – ARM cores support 32-bit ARM, 16-bit Thumb, and JVM (three software- visible ISAs) Joel Emer December 12, 2005 6.823, L25-9 Emulation • Software instruction set interpreter fetches and decodes one instruction at a time in emulated VM Emulator Stack Guest Memory image of Stack guest VM lives in host emulator data memory Executable on Disk Guest fetch-decode loop Load into ISA while(stop) Guest emulator Data ISA memory Data Guest inst = CodePC; ISA Guest Code PC += 4; ISA execute(inst); Code Emulator Data Emulator Code Joel Emer December 12, 2005 6.823, L25-10 Emulation • Easy to code, small code footprint • Slow, approximately 100x slower than native execution for RISC ISA hosted on RISC ISA • Problem is time taken to decode instructions – fetch instruction from memory – switch tables to decode opcodes – extract register specifiers using bit shifts – access register file data structure – execute operation – return to main fetch loop Joel Emer December 12, 2005 6.823, L25-11 Binary Translation • Each guest ISA instruction translates into some set of host (or native) ISA instructions • Instead of dynamically fetching and decoding instructions at run-time, translate entire binary program and save result as new native ISA executable • Removes interpretive fetch-decode overhead • Can optimize translated code to improve performance – register allocation for values flowing between guest ISA instructions – native instruction scheduling to improve performance – remove unreachable code – inline assembly procedures – remove dead code e.g., unneeded ISA side effects Joel Emer December 12, 2005 6.823, L25-12 Binary Translation, Take 1 Executable on Disk Data Guest Executable unchanged ISA on Disk Data Guest Native translation ISA Native might need extra data Data Data workspace Translate to native ISA code Guest Native ISA ISA Code Code Joel Emer December 12, 2005 6.823, L25-13 Binary Translation Problems Branch and Jump targets – guest code: j L1 ... L1: lw r1, (r4) jr (r1) –native code j translation native jump at end of block jumps to native translation of lw lw translation jr translation Where should the jump register go? Joel Emer December 12, 2005 6.823, L25-14 PC Mapping Table • Table gives translated PC for each guest PC • Indirect jumps translated into code that looks in table to find where to jump to – can optimize well-behaved guest code for subroutine call/return by using native PC in return links • If can branch to any guest PC, then need one table entry for every instruction in hosted program Î big table • If can branch to any PC, then either – limit inter-instruction optimizations – large code explosion to hold optimizations for each possible entry into sequential code sequence • Only minority of guest instructions are indirect jump targets, want to find these – design a highly structured VM design – use run-time feedback of target locations Joel Emer December 12, 2005 6.823, L25-15 Binary Translation Problems • Self-modifying code – sw r1, (r2) r2 points into code space • Rare in most code, but has to be handled if allowed by guest ISA • Usually handled by including interpreter and marking modified code pages as “interpret only” • Have to invalidate all native branches into modified code pages Joel Emer December 12, 2005 6.823, L25-16 Binary Translation, Take 2 Executable on Disk Guest ISA Data Keep copy of Mapping table used for code and indirect jumps and to data in native jump from emulator Guest ISA Executable data segment back into native Code on Disk translations Guest PC ISA Mapping Data Translation has to check Table for modified code pages Guest then jump to emulator ISA Native Translate to Code ISA Code native ISA code Emulator used for run­ time modified code, Native checks for jumps back Emulator into native code using PC mapping table Joel Emer December 12, 2005 6.823, L25-17 IBM System/38 and AS/400 • System/38 announced 1978, AS/400 is follow-on line • High-level instruction set interface designed for binary translation • Memory-memory style instruction set, never directly executed by hardware User Applications Languages, Control Database, Program Utilities Facility High-Level Architecture Interface Vertical Microcode Replaced by modified Used 48-bit CISC PowerPC cores in newer Horizontal Microcode engine in earlier AS/400 machines machines Hardware Machine Joel Emer December 12, 2005 6.823, L25-18 Dynamic Translation • Translate code sequences as needed at run­ time, but cache results • Can optimize code sequences based on dynamic information (e.g., branch targets encountered) • Tradeoff between optimizer run-time and time saved by optimizations in translated code • Technique used in Java JIT (Just-In-Time) compilers • Also, Transmeta Crusoe for x86 emulation Joel Emer December 12, 2005 6.823, L25-19 Dynamic Translation Example x86 Parser & x86 x86 High Level Translator Binary Binary Data RAM Disk Code Cache Code Cache High Level Tags Optimization Low Level Code Generation Low Level Optimization and Scheduling Translator Runtime Execution Joel Emer December 12, 2005 6.823, L25-20 Chaining Pre Chained add %r5, %r6, %r7 li %next_addr_reg, next_addr load address of next block Code CacheCode Cache j dispatch loop Tags Chained add %r5, %r6, %r7 j physical location of translated code for next_block Runtime -­ Execution

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