Logical architecture refinement ppt

logic micro operations computer architecture ppt and logic gates in computer architecture ppt
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Dr.ShawnPitt,Netherlands,Teacher
Published Date:25-07-2017
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L12: Reconfigurable Logic Architectures L12: Reconfigurable Logic Architectures Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Frank Honore Prof. Randy Katz (Unified Microelectronics Corporation Distinguished Professor in Electrical Engineering and Computer Science at the University of California, Berkeley) and Prof. Gaetano Borriello (University of Washington Department of Computer Science & Engineering) From Chapter 2 of R. Katz, G. Borriello. Contemporary Logic Design. 2nd ed. Prentice-Hall/Pearson Education, 2005. L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 1†††††††† „„„„„„„ History of Computational Fabrics History of Computational Fabrics Discrete devices: relays, transistors (1940s-50s) Discrete logic gates (1950s-60s) Integrated circuits (1960s-70s) e.g. TTL packages: Data Book for 100’s of different parts Gate Arrays (IBM 1970s) Transistors are pre-placed on the chip & Place and Route software puts the chip together automatically – only program the interconnect (mask programming) Software Based Schemes (1970’s- present) Run instructions on a general purpose core Programmable Logic (1980’s to present) A chip that be reprogrammed after it has been fabricated Examples: PALs, EPROM, EEPROM, PLDs, FPGAs Excellent support for mapping from Verilog ASIC Design (1980’s to present) Turn Verilog directly into layout using a library of standard cells Effective for high-volume and efficient use of silicon area L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 2†††††††† „„„„ Reconfigurable Logic Reconfigurable Logic Logic blocks To implement combinational and sequential logic Interconnect Wires to connect inputs and outputs to logic blocks I/O blocks Special logic blocks at periphery of device for external connections Key questions: How to make logic blocks programmable? (after chip has been fabbed) What should the logic granularity be? How to make the wires programmable? n m Logic SET D Q Logic (after chip has been fabbed) Inputs Outputs Q CLR Specialized wiring structures for local vs. long distance routes? How many wires per logic block? Configuration L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 3„„ Programmable Array Logic (PAL) Programmable Array Logic (PAL) Based on the fact that any combinational logic can be realized as a sum-of-products PALs feature an array of AND-OR gates with programmable interconnect AND input array signals OR array output signals programming of programming of product terms sum terms L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 4„„„ Inside the 22v10 PAL Inside the 22v10 PAL Each input pin (and its complement) sent to the AND array OR gates for each output can take 8-16 product terms, depending on output pin “Macrocell” block provides additional output flexibility... Image removed due to copyright restrictions. L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 5„ Cypress PAL CE22V10 Cypress PAL CE22V10 From Lattice Semiconductor Image removed due to copyright restrictions. Images courtesy of Lattice Semiconductor Corporation. Used with permission. Outputs may be registered or combinational, positive or inverted L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 6I/O Buffers, Programming and Test Logic Anti-Fuse-Based Approach (Actel) Anti-Fuse-Based Approach (Actel) I/O Buffers, Programming and Test Logic Rows of programmable logic building blocks + rows of interconnect Anti-fuse Technology: Program Once Use Anti-fuses to build I/O Buffers, Programming and Test Logic up long wiring runs from short segments Logic Module Wiring Tracks 8 input, single output combinational logic blocks FFs constructed from discrete cross coupled gates L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 7 I/O Buffers, Programming and Test LogicActel Logic Module Actel Logic Module Combinational block does not have the output FF Example Gate Mapping 00 GND 01 A Y 10 11 D E B C S-R Flip-Flop GND 00 01 VDD Q 10 11 S GND R VDD L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 8Actel Routing & Programming Actel Routing & Programming Courtesy of Actel. Used with permission. Precharge Phase Vpp/2 Vpp/2 Vpp/2 Input Segments Vpp/2 Inputs Outputs Gnd Vpp/2 Horizontal Vpp/2 Channel Vpp Logic Module Antifuse shorted Long Vertical Tracks Programming an Antifuse Output Segments Programming is Permanent (one time) Courtesy of Actel. Used with permission. L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 9RAM Based Field Programmable RAM Based Field Programmable Logic - Xilinx Logic - Xilinx Vcc Slew Passive Rate Pull-Up, Control Pull-Down CLB CLB D Q Switch Output Pad Buffer Matrix Input Buffer Q D Delay CLB CLB Programmable I/O Blocks (IOBs) Interconnect C1 C2 C3 C4 H1 DIN S/R EC S/R Control G4 DIN SD G F' G3 D Q G' Func. G2 H' Gen. G1 EC RD 1 G' H Y H' Func. S/R Control Gen. F4 F F3 DIN SD Func. F' Configurable F2 D Q G' Gen. H' F1 EC Logic Blocks (CLBs) RD 1 H' X F' K Courtesy of Xilinx. Used with permission. L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 10The Xilinx 4000 CLB The Xilinx 4000 CLB Courtesy of Xilinx. Used with permission. L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 11Two 4-input Functions, Registered Output Two 4-input Functions, Registered Output and a Two Input Function and a Two Input Function Courtesy of Xilinx. Used with permission. L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 125-input Function, Combinational Output 5-input Function, Combinational Output Courtesy of Xilinx. Used with permission. L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 13„„„ LUT Mapping LUT Mapping N-LUT direct implementation of a truth table: any function of n-inputs. N N-LUT requires 2 storage elements (latches) N-inputs select one latch location (like a memory) Inputs Why Latches and Not Registers? Courtesy of Xilinx. Output Used with permission. Latches set by configuration bitstream 4LUT example L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 14Configuring the CLB as a RAM Configuring the CLB as a RAM Memory is built using Latches not FFs Courtesy of Xilinx. Used with permission. 16x2 Read is same a LUT Function L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 15Xilinx 4000 Interconnect Xilinx 4000 Interconnect Courtesy of Xilinx. Used with permission. L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 16Xilinx 4000 Interconnect Details Xilinx 4000 Interconnect Details Wires are not ideal Courtesy of Xilinx. Used with permission. L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 17Xilinx 4000 Flexible IOB Xilinx 4000 Flexible IOB Adjust Transition Time Outputs through FF or bypassed Courtesy of Xilinx. Adjust the Sampling Edge Used with permission. L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 18Add Bells & Whistles Add Bells & Whistles Hard Processor Gigabit Serial I/O 18 Bit 36 Bit 18 Bit Multiplier VCCIO Z Z Programmable Impedance Z Clock Control Termination Mgmt BRAM Courtesy of David B. Parlour, ISSCC 2004 Tutorial, “The Reality and Promise of Reconfigurable Computing in Digital Signal Processing.” and Xilinx. Used with permission. L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 19The Virtex II CLB (Half Slice Shown) The Virtex II CLB (Half Slice Shown) Courtesy of Xilinx. Used with permission. L12: 6.111 Spring 2006 Introductory Digital Systems Laboratory 20

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