Memory hierarchy design ppt

memory system design ppt and cmos memory design ppt
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Published Date:25-07-2017
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Memory Design • Memory Types •Memoryg y Organization • ROM design • RAM desig gn • PLA design Adapted from J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital nd Integrated Circuits, 2 ed. Copyright 2003 Prentice Hall/Pearson. James Morizio ECE 261 1Semiconductor Semiconductor Memory Memory Classification Non-Volatile Read-Write Memory Read-Only Memory Read-Write Memory Random Non-Random EPROM Mask-Programmed Access Access 2 E E PROM PROM PPb rogrammablle (PROM)(PROM) FLASH FIFO SRAM LIFO DRAM DRAM Shift Register CAM James Morizio ECE 261 2MT Memory Tiimiing: DDefifiniitiions Read cy ycle READ Write Write cycle cycle Read access Read access WRITE Write Write access access Data valid DATA DATA Data written James Morizio ECE 261 3Memory y Architecture: M bits M bits Decoders SS SS 0 0 0 0 Word 0 Word 0 S 1 Word 1 Word 1 A 0 S Storage Storage 2 Word 2 Word 2 A 1 cell cell A words K 1 2 S N N 2 2 Decoder Word N 2 Word N 2 2 2 SS N 1 2 Word N 1 Word N 1 2 2 K log N 5 2 Input-Output Input-Output (M bits) (M bits) Intuitive architecture for N x M memory Decoder reduces the number of select signals Too many select signals: K = log N 2 2 NNd words == NN sellectt siignalls James Morizio ECE 261 4Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT WIDTH L 2K Bit line 2 Storage cell A K A K11 Word line A L21 K M. M.2 2 Amplify swing to Sense amplifiers / Drivers rail-to-rail amplitude A 0 0 Column decoder Selects appropriate A word K21 Inpp put-Output (M bits) James Morizio ECE 261 5 Row DecoderHierarchical Hierarchical Memory Memory Architecture Architecture Block 0 Block i Block P21 Row add ddress Column address Block address Global data bus Control Block selector Global circuitry amplifier/driver I/O Advantages: Advantages: 1. 1. 1. 1. Shorter Shorter Shorter Shorter wires wires wires wires within within within within b b blocks blocks locks locks 2. Block address activates only 1 block = 2. Block address activates only 1 block = power savings power savings James Morizio ECE 261 6RRd ead-Ol Only M Memory CCelllls BL BL BL V V DD WL WL WL 1 BL BL BL WL WL WL 0 GND Diode ROM MOS ROM 1 MOS ROM 2 James Morizio ECE 261 7MOS MOS O OR R R ROM OM BL0 BL1 BL2 BL3 WL0 V DD WL WL1 1 WL2 V DD WL3 V bias Pull-down loads James Morizio ECE 261 8ROM ROM Example Example • 4-word x 6-bit ROM Word 0: 010101 – Represented with dot diagram Word 1: 011001 – Dots indicate 1’s in ROM Word 2: 100101 w weak eak Word 3: 101010 101010 pseudo-nMOS A1 A0 pullups 2:4 DEC ROM Array y Y5 Y4 Y3 Y2 Y1 Y0 Looks Looks like like 6 6 4 4-input input pseudo pseudo-nMOS nMOS NORs NORs James Morizio ECE 261 9MOS MOS N NOR OR ROM ROM V DD Pull Pull-up up devices devices WL0 GND WL 1 WL 2 GND WL 3 BL BL 0 0 BL BL 1 1 BL BL 2 2 BL BL 3 3 James Morizio ECE 261 10MOS NOR ROM Layout Cell (9.5λ x 7λ) Programmming using the Active Layyy er Only Polysilicon Metal1 Diffusion Metal1 on Diffusion James Morizio ECE 261 11MOS NOR ROM Layout Cell Cell (1 (11 1λλ x7 x 7λλ) ) Programmming using the Contact Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion James Morizio ECE 261 12MOS NAND ROM V DD Pull-up devices BL0 BL1 BL2 BL3 WL0 WL1 WL2 WL3 All All w word ord lines lines high high by by default default w with ith exception exception of of selected selected row row James Morizio ECE 261 13MOS MOS NAND NAND ROM ROM L Layout ayout Cell (8λ x 7λ) Pi Programmming usi ing the Metal-1 Layer Only No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM Polysilicon Diffusion Metal1 on Diffusion James Morizio ECE 261 14NAND ROM Layout Cell (5λ x 6λ) PPi rogrammming usi ing Implants Only Polysilicon Threshold-altering implant implant Metal1 on Diffusion James Morizio ECE 261 15Decreasinggy Word Line Delay Driver WL Polysilicon word line Metal word line (a) Driving the word line from both sides Metal bypass WL K cells Polysilicon word line (b) Using a metal bypass James Morizio ECE 261 16Precharg ged MOS NOR ROM V DD f pre Precharge devices WL0 GND WL WL1 1 WL2 GND WL3 BL0 BL1 BL2 BL3 PMOS precharge device can be made as large as necessary, but but clock clock d driver river becomes becomes h harder arder to to design design. James Morizio ECE 261 17‰ ‰ Read-Write Memories (RAM) STATIC (SRAM) Dt Data st tored d as llong as supplly iis appl liid ed Large (6 transistors/cell) Fast Differential DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Single Ended Ended James Morizio ECE 261 186 6-transistor transistor CMOS CMOS SRAM SRAM Cell Cell WL WL V DD M M 2 2 4 4 Q M Q 6 M 5 M M 1 3 BL BL James Morizio ECE 261 196T-SRAM — Layout V DD M2 M4 Q Q M1 M1 M3 M3 GND M5 M5 M6 M6 WL BL BL James Morizio ECE 261 20

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