Combinational and sequential circuits ppt

combinational logic design ppt and difference between combinational and sequential circuits
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Published Date:26-07-2017
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Digital Logic Circuits Synthesis Fall 2015, Nov 6 . . . www.ThesisScientist.com 1Logic Synthesis • Definition: To design a logic circuit such that it meets the specifications and can be economically manufactured: • Performance – meets delay specification, or has minimum delay. • Cost – uses minimum hardware, smallest chip area, smallest number of gates or transistors. • Power – meets power specification, or consumes minimum power. • Testablility – has no redundant (untestable) logic and is easily testable. Fall 2015, Nov 6 . . . www.ThesisScientist.com 2Synthesis Procedure • Minimization – Obtain MSOP or MPOS. This is also known as two-level minimization because the result can be implemented as a two-level AND-OR or NAND-NAND or NOR-NOR circuit. • Technology mapping – Considering design requirements, transform the minimized form into one of the technologically realizable forms: • Programmable logic array (PLA) • Standard cell library • Field programmable gate array (FPGA) • Others . . . Fall 2015, Nov 6 . . . www.ThesisScientist.com 3References on Synthesis • G. De Micheli, Synthesis and Optimization of Digital Circuits, New York: McGraw-Hill, 1994. • S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill, 1994. Fall 2015, Nov 6 . . . www.ThesisScientist.com 4Programmable Logic Array (PLA) • A direct implementation of multi-output function as a two-level circuit in MOS technology. • PLA styles: • NAND-NAND • NOR-NOR • Textbook, Chapter 5. Fall 2015, Nov 6 . . . www.ThesisScientist.com 5Example: Two-Output Function Need four products: P1, P2, P3, P4 A A F1 F2 0 4 12 8 0 4 12 8 1 1 5 13 9 1 5 13 9 1 1 1 1 1 1 D D 3 7 15 11 3 7 15 11 1 1 1 1 1 C C 2 6 14 10 2 6 14 10 1 B B Fall 2015, Nov 6 . . . www.ThesisScientist.com 6Two-Level AND-OR Implementation • Also known as technology-independent circuit. INPUTS AND OR C P1 F1 P2 A P3 F2 B P4 D Fall 2015, Nov 6 . . . www.ThesisScientist.com 7NAND-NAND Implementation INPUTS NAND NAND C P1 F1 P2 A P3 F2 B D P4 Fall 2015, Nov 6 . . . www.ThesisScientist.com 8A NAND Gate in nMOS Technology VDD VDD VDD Enhancement Depletion load load XY XY XY X X X Y Y Y GND GND GND R. C. Jaeger and T, N. Blalock, Microelectronic Circuit Design, Boston: McGraw-Hill, 2008, Section 6.8.2. Fall 2015, Nov 6 . . . www.ThesisScientist.com 9NAND-NAND PLA A B C D F1 F2 VDD VDD VDD P1 VDD P2 VDD P3 VDD P4 GND Fall 2015, Nov 6 . . . www.ThesisScientist.com 10NAND-NAND PLA SCHEMATIC A B C D F1 F2 P1 P2 P3 P4 AND-plane OR-plane Fall 2015, Nov 6 . . . www.ThesisScientist.com 11 Transistors at cross-points INPUTS OUTPUTSStandard-Cell Design • Obtain two-level minimized form. • Map the design onto predesigned building blocks called standard cells (technology mapping). • Standard-cell library contains predesigned logic cells in the technology of manufacture. Examples of technology: • 90 nanometer CMOS • 65 nanometer CMOS • 45 nanometer CMOS • . . . • This is known as application-specific integrated circuit (ASIC). Fall 2015, Nov 6 . . . www.ThesisScientist.com 12Technology Mapping • Find a common logic element, e.g., two-input NAND gate or inverter (one-input NAND). • MSOP is converted into NAND-NAND circuit. • Split larger input gates into two-input NAND gates and inverters. • Cover the circuit with standard cells, also split into two-input NAND gates and inverters (graph- matching). Fall 2015, Nov 6 . . . www.ThesisScientist.com 13A Typical Cell Library Name Area units (cost) Inputs Output function, Z Inverter 2 A Z A NAND2 3 A, B Z AB NAND3 4 A, B, C Z ABC NAND4 5 A, B, C, D Z ABCD AOI21 4 A, B, C Z ABC OAI21 4 A, B, C Z  (A B)C AOI22 5 A, B, C, D Z ABCD XOR 4 A, B Z ABAB S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill 1994, Section 7.7, pp. 185-198. Fall 2015, Nov 6 . . . www.ThesisScientist.com 14NAND3 Cell in Transistors VDD Z A B C GND Fall 2015, Nov 6 . . . www.ThesisScientist.com 15NAND3 Cell Graphs Directed Acyclic Graph (DAG) (tree) Root ≡ Output One-input node (NOT) Two-input node (NAND) Fall 2015, Nov 6 . . . www.ThesisScientist.com 16NAND4 Cell Fall 2015, Nov 6 . . . www.ThesisScientist.com 17AOI21 Cell Fall 2015, Nov 6 . . . www.ThesisScientist.com 18OAI21 Cell Fall 2015, Nov 6 . . . www.ThesisScientist.com 19AOI22 Cell in Transistors VDD Pull-up network A Z B C Pull-down network D GND Observe that in a CMOS circuit, any vector of input variables connects the output Z either to GND or to VDD, giving it a value 0 or 1, respectively. Examining the pull-down network, we notice that the output is connected to GND if AB = 1 or CD =1. That gives the output function as, . The cell, therefore, is AOI22. Z ABCD Fall 2015, Nov 6 . . . www.ThesisScientist.com 20

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