clock synchronization ppt

process synchronization ppt and synchronization in digital communication ppt
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Published Date:25-07-2017
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L6: FSMs and Synchronization L6: FSMs and Synchronization Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Rex Min , 2003. J. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice Hall/Pearson, 2003. L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 1Asynchronous Inputs in Sequential Systems Asynchronous Inputs in Sequential Systems What about external signals? Can’t guarantee Sequential System setup and hold times will be met Clock When an asynchronous signal causes a setup/hold violation... I II III ? Q D Clock Output is metastable Transition is missed Transition is caught for an indeterminate on first clock cycle, on first clock cycle. amount of time. but caught on next clock cycle. Q: Which cases are problematic? Courtesy of Nathan Ickes. Used with permission. L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 2Asynchronous Inputs in Sequential Systems Asynchronous Inputs in Sequential Systems All of them can be, if more than one happens simultaneously within the same circuit. Idea: ensure that external signals directly feed exactly one flip-flop Clocked Synchronous System Q0 Async D Q Input Sequential System DQ Clock Q1 D Q Clock Clock Courtesy of Nathan Ickes. Used with permission. This prevents the possibility of I and II occurring in different places in the circuit, but what about metastability? L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 3„„ „„„ Handling Metastability Handling Metastability Preventing metastability turns out to be an impossible problem High gain of digital devices makes it likely that metastable conditions will resolve themselves quickly Solution to metastability: allow time for signals to stabilize Likely to be Very unlikely to Extremely unlikely metastable be metastable for to be metastable for right after 1 clock cycle 2 clock cycle sampling Complicated DQ DQ DQ Sequential Logic System Clock How many registers are necessary? Depends on many design parameters(clock speed, device speeds, …) In 6.111, one or maybe two synchronization registers is sufficient L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 4„„ Finite State Machines Finite State Machines Finite State Machines (FSMs) are a useful abstraction for sequential circuits with centralized “states” of operation At each clock edge, combinational logic computes outputs and next state as a function of inputs and present state Combinational inputs outputs Logic + + present next state state n n Q D Flip- Flops CLK L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 5Two Types of FSMs Two Types of FSMs Moore and Mealy FSMs are distinguished by their output generation Moore FSM: next state + S inputs outputs D Q Comb. Flip- Comb. n x ...x 0 n y = f (S) Logic Flops Logic k k CLK n present state S Mealy FSM: direct combinational path outputs y = f (S, x ...x ) k k 0 n + inputs S Comb. Q D Comb. Flip- x ...x Logic 0 n n Logic Flops CLK n S L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 6†† „„„ Design Example: Level-to-Pulse Design Example: Level-to-Pulse A level-to-pulse converter produces a single-cycle pulse each time its input goes high. In other words, it’s a synchronous rising- edge detector. Sample uses: Buttons and switches pressed by humans for arbitrary periods of time Single-cycle enable signals for counters Level to LP Pulse Converter ...output P produces a Whenever input L goes single pulse, one clock from low to high... period wide. CLK L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 7„„ State Transition Diagrams State Transition Diagrams Block diagram of desired system: Synchronizer Edge Detector Level to unsynchronized DQ DQ LP Pulse user input FSM CLK State transition diagram is a useful FSM representation and design aid “if L=1 at the clock edge, L=1 Binary values of states L=1 then jump to state 01.” 11 00 01 L=0 Low input, High input, Edge Detected L=1 Waiting for rise Waiting for fall P = 1 P = 0 P = 0 L=0 L=0 This is the output that results from “if L=0 at the clock edge, this state. (Moore or Mealy?) then stay in state 00.” L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 8„„ Logic Derivation for a Moore FSM Logic Derivation for a Moore FSM Transition diagram is readily converted to a Current Next In Out state transition table (just a truth table) State State + + S S L S S P 1 0 1 0 L=1 L=1 0 0 0 0 0 0 L=0 L=1 0 0 1 0 1 0 00 11 01 Low input, High input, 0 1 0 0 0 1 Edge Detected Waiting for rise Waiting for fall P = 1 0 1 1 1 1 1 P = 0 P = 0 L=0 1 1 0 0 0 0 L=0 1 1 1 1 1 0 Combinational logic may be derived by Karnaugh maps + for S : S S 1 1 0 00 01 11 10 L 0 0 0 0 X + S 1 0 1 1 X L P Q D Comb. Flip- Comb. for P: n S Logic Flops Logic + 1 for S : 0 S S S 0 1 CLK 1 0 0 n 00 01 11 10 L 0 0 X 0 0 0 0 X S 1 1 0 + + P = S S S = LS P = S S S = LS 1 0 1 0 1 0 1 1 1 1 X 1 0 + + S = L S = L 0 0 L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 9Moore Level-to-Pulse Converter Moore Level-to-Pulse Converter next state + S inputs outputs D Q Comb. Flip- Comb. n x ...x 0 n y = f (S) Logic Flops Logic k k CLK n present state S + + S = LS S = LS 1 0 1 0 P = S S P = S S 1 0 + 1 0 + S = L S = L 0 0 Moore FSM circuit implementation of level-to-pulse converter: + S S 0 0 DQ L P CLK Q DQ + S S 1 1 Q L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 10„ Design of a Mealy Level-to-Pulse Design of a Mealy Level-to-Pulse direct combinational path + S Comb. Q D Comb. Flip- Logic n Logic Flops CLK n S Since outputs are determined by state and inputs, Mealy FSMs may need fewer states than Moore FSM implementations 1. When L=1 and S=0, this output is asserted immediately and until the L state transition occurs (or L changes). 1 2 P L=1 P=1 Clock 0 1 L=0 P=0 State Input is low Input is high Output transitions L=0 P=0 immediately. L=1 P=0 State transitions at the clock edge. 2. After the transition to S=1 and as long as L remains at 1, this output is 0. L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 11„„ Mealy Level-to-Pulse Converter Mealy Level-to-Pulse Converter Pres. Next In Out State State L=1 P=1 + S L S P 0 1 0 0 0 0 Input is low Input is high 0 1 1 1 L=0 P=0 1 0 0 0 L=0 P=0 L=1 P=0 1 1 1 0 Mealy FSM circuit implementation of level-to-pulse converter: P + S S DQ L CLK Q S FSM’s state simply remembers the previous value of L Circuit benefits from the Mealy FSM’s implicit single-cycle assertion of outputs during state transitions L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 12††††† „„ Moore/Mealy Trade-Offs Moore/Mealy Trade-Offs Remember that the difference is in the output: Moore outputs are based on state only Mealy outputs are based on state and input Therefore, Mealy outputs generally occur one cycle earlier than a Moore: Moore: delayed assertion of P Mealy: immediate assertion of P L L P P Clock Clock State0 State Compared to a Moore FSM, a Mealy FSM might... Be more difficult to conceptualize and design Have fewer states L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 13„ Review: FSM Timing Requirements Review: FSM Timing Requirements Timing requirements for FSM are identical to any generic sequential system with feedback Minimum Clock Period Minimum Delay Combinational Combinational inputs inputs outputs outputs Logic Logic + + + + present present next next T state logic state state state T logic,cd n n n n T T cq cq,cd Q D Q D Flip- Flip- T T hold su Flops Flops CLK CLK T T + T T T T + T + T cq,cd logic,cd hold cq logic su L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 14†††††† „„„„„ The 6.111 Vending Machine The 6.111 Vending Machine Lab assistants demand a new soda machine for the 6.111 lab. You design the FSM controller. 30¢ 30¢ All selections are 0.30. COINS ONLY The machine makes change. 25¢ 5¢ 10¢ (Dimes and nickels only.) Co Inputs: limit 1 per clock Sprite Q - quarter inserted Jolt D - dime inserted Water N - nickel inserted LS163 Outputs: limit 1 per clock DC - dispense can DD - dispense dime DN - dispense nickel L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 15„„„„ What States are in the System? What States are in the System? A starting (idle) state: idle A state for each possible amount of money captured: ... got5c got10c got15c What’s the maximum amount of money captured before purchase? 25 cents (just shy of a purchase) + one quarter (largest coin) ... got35c got40c got45c got50c States to dispense change (one per coin dispensed): Dispense Dispense got45c Dime Nickel L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 16A Moore Vender A Moore Vender idle Here’s a first cut at the N=1 state transition diagram. D=1 got5c N=1 Q=1 D=1 got10c N=1 got15c D=1 N=1 Q=1 got20c D=1 N=1 Q=1 got25c D=1 Q=1 N=1 See a better way? got30c D=1 So do we. DC=1 Q=1 Don’t go away... chg35 got35c DN=1 DC=1 chg40 got40c DD=1 DC=1 chg45 chg45b got45c DD=1 DN=1 DC=1 got50c chg50 chg50b DD=1 DD=1 DC=1 L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 17„„ „„ State Reduction State Reduction idle Duplicate states have: Duplicate states have: N=1 The same outputs, and The same outputs, and idle D=1 got5c The same transitions The same transitions N=1 N=1 There are two duplicates There are two duplicates D=1 got5c Q=1 D=1 got10c in our original diagram. in our original diagram. N=1 N=1 Q=1 D=1 got10c got15c D=1 N=1 N=1 Q=1 D=1 got15c got20c N=1 Q=1 D=1 D=1 got20c N=1 Q=1 N=1 got25c D=1 Q=1 D=1 got25c N=1 Q=1 N=1 got30c Q=1 D=1 got30c D=1 DC=1 DC=1 Q=1 Q=1 rtn5 got35c chg35 got35c 17 states 15 states DN=1 DC=1 DN=1 DC=1 5 state bits 4 state bits chg40 got40c rtn10 got40c DC=1 DD=1 DD=1 DC=1 chg45 chg45b got45c rtn15 got45c DD=1 DN=1 DC=1 DD=1 DC=1 got50c chg50 chg50b DC=1 DD=1 DD=1 got50c rtn20 DD=1 DC=1 L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 18„„„ Verilog for the Moore Vender Verilog for the Moore Vender module mooreVender (N, D, Q, DC, DN, DD, clk, reset, state); input N, D, Q, clk, reset; output DC, DN, DD; Q D Comb. State Comb. output 3:0 state; n Logic Register Logic reg 3:0 state, next; CLK n States defined with parameter keyword parameter IDLE = 0; parameter GOT_5c = 1; FSMs are easy in Verilog. parameter GOT_10c = 2; parameter GOT_15c = 3; parameter GOT_20c = 4; Simply write one of each: parameter GOT_25c = 5; parameter GOT_30c = 6; parameter GOT_35c = 7; State register parameter GOT_40c = 8; (sequential always block) parameter GOT_45c = 9; parameter GOT_50c = 10; parameter RETURN_20c = 11; Next-state parameter RETURN_15c = 12; combinational logic parameter RETURN_10c = 13; parameter RETURN_5c = 14; (comb. always block with case) State register defined with sequential Output combinational always block logic block always (posedge clk or negedge reset) (comb. always block orassign if (reset) state = IDLE; statements) else state = next; L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 19Verilog for the Moore Vender Verilog for the Moore Vender GOT_25c: if (Q) next = GOT_50c; Next-state logic within a else if (D) next = GOT_35c; else if (N) next = GOT_30c; combinational always block else next = GOT_25c; GOT_30c: next = IDLE; always (state or N or D or Q) begin GOT_35c: next = RETURN_5c; GOT_40c: next = RETURN_10c; case (state) GOT_45c: next = RETURN_15c; IDLE: if (Q) next = GOT_25c; GOT_50c: next = RETURN_20c; else if (D) next = GOT_10c; else if (N) next = GOT_5c; RETURN_20c: next = RETURN_10c; else next = IDLE; RETURN_15c: next = RETURN_5c; RETURN_10c: next = IDLE; GOT_5c: if (Q) next = GOT_30c; RETURN_5c: next = IDLE; else if (D) next = GOT_15c; else if (N) next = GOT_10c; default: next = IDLE; else next = GOT_5c; endcase end GOT_10c: if (Q) next = GOT_35c; else if (D) next = GOT_20c; else if (N) next = GOT_15c; Combinational output assignment else next = GOT_10c; GOT_15c: if (Q) next = GOT_40c; assign DC = (state == GOT_30c state == GOT_35c else if (D) next = GOT_25c; state == GOT_40c state == GOT_45c else if (N) next = GOT_20c; state == GOT_50c); else next = GOT_15c; assign DN = (state == RETURN_5c); assign DD = (state == RETURN_20c state == RETURN_15c GOT_20c: if (Q) next = GOT_45c; state == RETURN_10c); else if (D) next = GOT_30c; endmodule else if (N) next = GOT_25c; else next = GOT_20c; L6: 6.111 Spring 2006 Introductory Digital Systems Laboratory 20

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