Introduction to vhdl programming ppt

vhdl data types ppt and vhdl libraries and packages ppt
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Prof.SteveBarros,United Kingdom,Teacher
Published Date:28-07-2017
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VHDLINTRODUCTION § The VHSIC Hardware Description Language (VHDL) is an industry standard language used to describe hardware from the abstract to concrete level. § The language not only defines the syntax but also defines very clear simulation semantics for each language construct. § It is strong typed language and is often verbose to write. § Provides extensive range of modeling capabilities,it is possible to quickly assimilate a core subset of the language that is both easy and simple to understand without learning the more complex features.Why Use VHDL? § Quick Time-to-Market • Allows designers to quickly develop designs requiring tens of thousands of logic gates • Provides powerful high-level constructs for describing complex logic • Supports modular design methodology and multiple levels of hierarchy § One language for design and simulation § Allows creation of device-independent designs that are portable to multiple vendors. Good for ASIC Migration § Allows user to pick any synthesis tool, vendor, or deviceBASIC FEATURES OF VHDL § CONCURRENCY. § SUPPORTS SEQUENTIAL STATEMENTS. § SUPPORTS FOR TEST & SIMULATION. § STRONGLY TYPED LANGUAGE. § SUPPORTS HIERARCHIES. § SUPPORTS FOR VENDOR DEFINED LIBRARIES. § SUPPORTS MULTIVALUED LOGIC.CONCURRENCY § VHDL is a concurrent language. § HDL differs with Software languages with respect to Concurrency only. § VHDL executes statements at the same time in parallel,as in Hardware.SUPPORTS SEQUENTIAL STATEMENTS § VHDL supports sequential statements also, it executes one statement at a time in sequence only. § As the case with any conventional languages. example: if a=‘1’ then y=‘0’; else y=‘1’; end if ;SUPPORTS FOR TEST & SIMULATION. § To ensure that design is correct as per the specifications, the designer has to write another program known as “TEST BENCH”. § It generates a set of test vectors and sends them to the design under test(DUT). § Also gives the responses made by the DUT against a specifications for correct results to ensure the functionality.STRONGLY TYPED TYPED LANGUAGE LANGUAGE § VHDL allows LHS & RHS operators of same type. § Different types in LHS & RHS is illegal in VHDL. § Allows different type assignment by conversion. example: A : in std_logic_vector(3 downto 0). B : out std_logic_vector(3 downto 0). C : in bit_vector(3 downto 0). B = A; perfect. B = C; type miss match,syntax error.SUPPORTS HIRERCHIES HIRERCHIES § Hierarchy can be represented using VHDL. § Consider example of a Full-adder which is the top-level module, being composed of three lower level modules i.e. Half-Adder and OR gate. example : SUM A Half-adder Half-adder carry B Or-gate CLEVELS OF ABSTRACTION § Data Flow level • In this style of modeling the flow of data through the entity is expressed using concurrent signal assignment statements. § Structural level • In this style of modeling the entity is described as a set of interconnected statements. § Behavioral level. • This style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specified order.EXAMPLE SHOWING ABSTRACTION LEVELS entity full_adder is port(a,b,c:in bit;sum,cout:out bit); structure end full_adder; dataflow architecture fulladd_mix of full_adder is a s1 x1 component xor2 b sum port(p1,p2:in bit; pz:out bit); end component; c signal s1:bit; begin x1:xor2 port map(a,b,s1); process(a,b,c) variable t1,t2,t3:bit; cout begin t1:=a and b; t2:=b and cin; t3:=a and cin; cout = t1 or t2 or t3; behavior end process sum = s1 xor cin; end fulladd_mix;VHDL VHDL IDENTIFIERS § Identifiers are used to name items in a VHDL model. § A basic identifier may contain only capital ‘A’ - ’Z’ , ‘a’ - ’z’, ‘0’ - ’9’, underscore character ‘_’ § Must start with a alphabet. § May not end with a underscore character. § Must not include two successive underscore characters. § Reserved word cannot be used as identifiers. § VHDL is not case sensitive. OBJECTS § There are three basic object types in VHDL • Signal : represents interconnections that connect components and ports. • Variable : used for local storage within a process. • Constant : a fixed value. § The object type could be a scalar or an array.DATA DATA TYPES IN IN VHDL VHDL § Type • Is a name which is associated with a set of values and a set of operations. § Major types: • Scalar Types • Composite TypesSCALAR TYPES TYPES § Integer Maximum range of integer is tool dependent type integer is range implementation_defined constant loop_no : integer := 345; Signal my_int : integer range 0 to 255; § Floating point • Can be either positive or negative. • exponents have to be integer. type real is range implementation_definedSCALAR SCALAR TYPES TYPES (Cont..) (Cont..) § Physical Predefined type “Time” used to specify delays. Example : type TIME is range -2147483647 to 2147483647 § Enumeration Values are defined in ascending order. Example: type alu is ( pass, add, subtract, multiply,divide )COMPOSITE TYPES TYPES § There are two composite types § ARRAY : • Contain many elements of the same type. • Array can be either single or multidimensional. • Single dimensional array are synthesizable. • The synthesis of multidimensional array depends upon the synthesizer being used. § RECORD :Contain elements of different types.THE THE STD_LOGIC TYPE _LOGIC TYPE § It is a data type defined in the std_logic_1164 package of IEEE library. § It is an enumerated type and is defined as type std_logic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’,’-’) ‘u’ unspecified ‘x’ unknown ‘0’ strong zero ‘1’ strong one ‘z’ high impedance ‘w’ weak unknown ‘l’ weak zero ‘h’ weak one ‘-’ don’t careALIAS § Alias is an alternative name assigned to part of an object simplifying its access. Syntax : alias alias_name : subtype is name; Examples: signal inst : std_logic_vector(7 downto 0); alias opcode : std_logic_vector(3 downto 0) is inst (7 downto 4); alias srce : std_logic_vector(1 downto 0)is inst (3 downto 2); alias dest : std_logic_vector(1 downto 0) is inst (1 downto 0);SIGNAL SIGNAL ARRAY § A set of signals may also be declared as a signal array which is a concatenated set of signals. § This is done by defining the signal of type bit_vector or std_logic_vector. § bit_vector and std_logic_vector are types defined in the ieee.std_logic_1164 package. § Signal array is declared as : type(range) Example: signal data1:bit_vector(1 downto 0) signal data2: std_logic_vector(7 down to 0); signal address : std_logic_vector(0 to 15);

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