Embedded processors ppt

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Published Date:23-07-2017
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Lecture 11: Interfaces, I/O and Configurable Processors Professor Kurt Keutzer Computer Science 252 Spring 2000 With contributions from Prof. David Patterson Niraj Shah, Scott Weber 1 Kurt KeutzerEmbedded Systems vs. General Purpose Computing - 1 Embedded System General purpose computing • Runs a few applications often •Intended to run a fully general known at design time set of applications • Not end-user programmable • End-user programmable • Operates in fixed run-time • Faster is always better constraints, additional performance may not be useful/valuable 2 Kurt KeutzerEmbedded Systems vs. General Purpose Computing - 2 Embedded System General purpose computing Differentiating features: Differentiating features  power  speed (need not be fully predictable)  cost  speed  speed (must be predictable)  did we mention speed?  cost (largest component power) 3 Kurt KeutzerConfigurabilty and Embedded Systems Advantages of configuration: • Pay (in power, design time, area) only for what you use • Gain additional performance by adding features tailored to your application: Particularly for embedded systems:  Principally in embedded controller microprocessor applications  Some us in DSP 4 Kurt KeutzerWhat to Configure? What parts of the microcontroller/microprocessor system to configure? Easy answers: • Memory and Cache Sizes - get precisely the sizes your applications needs • Register file sizes • Interrupt handling and addresses Harder answers: • Peripherals • Instructions But first we need more context 5 Kurt KeutzerI/O Interrupts An I/O interrupt is just like the exception handlers except:  An I/O interrupt is asynchronous  Further information needs to be conveyed An I/O interrupt is asynchronous with respect to instruction execution:  I/O interrupt is not associated with any instruction  I/O interrupt does not prevent any instruction from completion  You can pick your own convenient point to take an interrupt I/O interrupt is more complicated than exception:  Needs to convey the identity of the device generating the interrupt  Interrupt requests can have different urgencies:  Interrupt request needs to be prioritized 6 Kurt KeutzerRestore PC User Mode Example: Device Interrupt Raise priority Reenable All Ints ………… Save registers add r1,r2,r3 ………… subi r4,r1,4 lw r1,20(r0) slli r4,r4,2 lw r2,0(r1) addi r3,r0,5 Hiccup() sw r3,0(r1) …… lw r2,0(r4) …… Restore registers lw r3,4(r4) Clear current Int add r2,r2,r3 Disable All Ints sw 8(r4),r2 ………… Restore priority RTI Advantage:  User program progress is only halted during actual transfer Disadvantage, special hardware is needed to:  Cause an interrupt (I/O device)  Detect an interrupt (processor)  Save the proper states to resume after the interrupt (processor) 7 Kurt Keutzer PC saved Disable All Ints Supervisor Mode External Interrupt “Interrupt Handler”Interrupt Driven Data Transfer CPU add sub user (1) I/O and program interrupt or nop (2) save PC Memory IOC (3) interrupt device service addr read interrupt store User program progress only halted during service ... actual transfer routine (4) rti 1000 transfers at 1 ms each: memory 1000 interrupts 2 µsec per interrupt 1000 interrupt service 98 µsec each = 0.1 CPU seconds -6 Device xfer rate = 10 MBytes/sec = 0 .1 x 10 sec/byte = 0.1 µsec/byte = 1000 bytes = 100 µsec 1000 transfers x 100 µsecs = 100 ms = 0.1 CPU seconds Still far from device transfer rate 1/2 in interrupt overhead 8 Kurt KeutzerBetter Way to Handle Interrupts? Handling all interrupts with CPU could bring it to a halt in a real time system Isn’t there a better way? Hint, remember the trickledown theory of embedded processor architecture. 9 Kurt KeutzerTrickle Down Theory of Embedded Architectures Features tend to trickle Mainframe/supercomputers down: • bits: 4-8-16-32-64 • ISA’s High-end servers/workstations • Floating point support • Dynamic scheduling • Caches • I/O controllers/processors High-end personal computers • LIW/VLIW • Superscalar Personal computers Lap tops/palm tops 10 Kurt Keutzer GadgetsI/O Interface CPU Memory memory Independent I/O Bus bus Separate I/O instructions (in,out) Interface Interface Peripheral Peripheral CPU Lines distinguish between I/O and memory transfers common memory & I/O bus 40 Mbytes/sec optimistically VME bus Multibus-II Memory Interface Interface 10 MIP processor Nubus completely saturates the bus Peripheral Peripheral 11 Kurt KeutzerDelegating I/O Responsibility from the CPU: IOP D1 IOP CPU D2 main memory bus . . . Mem Dn I/O target device bus where cmnds are OP Device Address CPU (1) Issues (4) IOP interrupts instruction CPU when done IOP IOP looks in memory for commands to IOP (2) OP Addr Cnt Other (3) memory what special Device to/from memory to do requests transfers are controlled where how by the IOP directly. to put much data IOP steals memory cycles. 12 Kurt KeutzerMemory Mapped I/O CPU Single Memory & I/O Bus No Separate I/O Instructions ROM RAM Memory Interface Interface Peripheral Peripheral CPU I/O L2 Memory Bus I/O bus Memory Bus Adaptor 13 Kurt KeutzerDelegating I/O Responsibility from the CPU: DMA CPU sends a starting address, direction, and length count to DMAC. Then issues "start". Direct Memory Access (DMA): CPU  External to the CPU  Act as a master on the bus  Transfers blocks of data to or from memory without CPU Memory DMAC IOC intervention device DMAC provides handshake signals for Peripheral Controller, and Memory Addresses and handshake signals for Memory. 14 Kurt KeutzerDirect Memory Access Time to do 1000 xfers at 1 msec each: 1 DMA set-up sequence 50 µsec CPU sends a starting address, 1 interrupt 2 µsec direction, and length count to 1 interrupt service sequence 48 µsec DMAC. Then issues "start". .0001 second of CPU time 0 ROM CPU Memory Mapped I/O RAM DMAC Memory IOC device Peripherals DMAC provides handshake signals for Peripheral Controller, and Memory Addresses and handshake signals for Memory. DMAC n 15 Kurt Keutzer68332 Family 68K was the most successful embedded controller in history CISC instruction set - good code density Table lookup for compressed tables Time processing unit - breakthrough in modular peripheral handling 16 Kurt KeutzerMC68332 - Top level IMB inter module bus I/0 - channel 0 time CPU32 processing unit TPU I/0 - channel 15 serial I/0 RAM IMB control Designed for automotive applications with mixture of computation intensive tasks and complex I/0 -functions Idea: off-load CPU from frequent I/0 interactions to make use of computation performance: TPU 17 Kurt Keutzer68332 CPU Block Diagram 18 Kurt KeutzerAddressing Modes in 68332 Seven modes • Register direct • Register indirect • Register indirect with index • Program counter indirect with displacement • Program counter indirect with Index • Absolute • Immediate Why so many modes? Antiquated architectural feature? 19 Kurt KeutzerAddressing Modes in 68332 Seven modes • Register direct • Register indirect • Register indirect with index • Program counter indirect with displacement • Program counter indirect with Index • Absolute • Immediate Complex addressing modes allow for more dense code … but … MCore - Mot’s embedded micocontroller rewrite uses simple DLX-like Load Store instructions - code size impact? 20 Kurt Keutzer

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