Combinational logic circuits ppt

combinational logic design ppt and combinational logic ppt
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Published Date:25-07-2017
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L3: Introduction to Verilog L3: Introduction to Verilog (Combinational Logic) (Combinational Logic) Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Rex Min Verilog References: • Samir Palnitkar, Verilog HDL, Pearson Education (2nd edition). • Donald Thomas, Philip Moorby, The Verilog Hardware Description Language, Fifth Edition, Kluwer Academic Publishers. • J. Bhasker, Verilog HDL Synthesis (A Practical Primer), Star Galaxy Publishing L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory„„„ „ Synthesis and HDLs Synthesis and HDLs Hardware description language (HDL) is a convenient, device- independent representation of digital logic Verilog input a,b; output sum; assign sum = 1b’0, a + 1b’0, b; HDL description is compiled Compilation and into a netlist Synthesis Netlist Synthesis optimizes the logic g1 "and" n1 n2 n5 g2 "and" n3 n4 n6 g3 "or" n5 n6 n7 Mapping targets a specific hardware platform Mapping ASIC FPGA PAL (Custom ICs) 5 L3: 6.111 Spring 200 Introductory Digital Systems Laboratory„„ The FPGA: A Conceptual View The FPGA: A Conceptual View An FPGA is like an electronic breadboard that is wired together by an automated synthesis tool Built-in components are called macros 32 32 DQ SUM + 32 sel counter interconnect a F(a,b,c,d) b LUT c G(a,b,c,d) d ADR DATA RAM R/W (for everything else) 6 L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory„„ Synthesis and Mapping for FPGAs Synthesis and Mapping for FPGAs Infer macros: choose the FPGA macros that efficiently implement various parts of the HDL code ... “This section of code looks always (posedge clk) like a counter. My FPGA has begin some of those...” counter count = count + 1; end ... HDL Code Inferred Macro Place-and-route: with area and/or speed in mind, choose the needed macros by location and route the interconnect M M M M M M M “This design only uses 10% of M M M M M M M the FPGA. Let’s use the macros M M M M M M M in one corner to minimize the M M M M M M M distance between blocks.” M M M M M M M 7 L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory„„„ Verilog: The Module Verilog: The Module Verilog designs consist of a 1 interconnected modules. out A module can be an element or b 0 outbar collection of lower level design blocks. sel A simple module with combinational logic might look like this: Out = sel● a + sel● b 2-to-1 multiplexer with inverted output module mux_2_to_1(a, b, out, Declare and name a module; list its ports. Don’t forget that semicolon. outbar, sel); Comment starts with // // This is 2:1 multiplexor Verilog skips from // to end of the line input a, b, sel; Specify each port as input, output, or inout output out, outbar; Express the module’s behavior. assign out = sel ? a : b; Each statement executes in assign outbar = out; parallel; order does not matter. Conclude the module code. endmodule L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 8†††† „„„„„„„ Continuous (Dataflow) Assignment Continuous (Dataflow) Assignment module mux_2_to_1(a, b, out, outbar, sel); a 1 input a, b, sel; out output out, outbar; b 0 outbar assign out = sel ? a : b; assign outbar = out; sel endmodule Continuous assignments use the assign keyword A simple and natural way to represent combinational logic Conceptually, the right-hand expression is continuously evaluated as a function of arbitrarily-changing inputs…just like dataflow The target of a continuous assignment is a net driven by combinational logic Left side of the assignment must be a scalar or vector net or a concatenation of scalar and vector nets. It can’t be a scalar or vector register (discussed later). Right side can be register or nets Dataflow operators are fairly low-level: Conditional assignment: (conditional_expression) ? (value-if-true) : (value-if-false); Boolean logic: , &, Arithmetic: +, -, Nested conditional operator (4:1 mux) assign out = s1 ? (s0 ? i3 : i2) : (s0? i1 : i0); L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 9††† „„ Gate Level Description Gate Level Description module muxgate (a, b, out, outbar, sel); input a, b, sel; a output out, outbar; out1 sel wire out1, out2, selb; and a1 (out1, a, sel); out not i1 (selb, sel); outbar and a2 (out2, b , selb); selb out2 or o1 (out, out1, out2); b assign outbar = out; endmodule Verilog supports basic logic gates as primitives and, nand, or, nor, xor, xnor, not, buf can be extended to multiple inputs: e.g., nand nand3in (out, in1, in2,in3); bufif1 and bufif0 are tri-state buffers Net represents connections between hardware elements. Nets are declared with the keyword wire. L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 10„„„ Procedural Assignment with always Procedural Assignment with always Procedural assignment allows an alternative, often higher-level, behavioral description of combinational logic Two structured procedure statements: initial and always Supports richer, C-like control structures such as if, for, while,case module mux_2_to_1(a, b, out, outbar, sel); Exactly the same as before. input a, b, sel; output out, outbar; Anything assigned in an always reg out, outbar; block must also be declared as type reg (next slide) Conceptually, the always block always (a or b or sel) runs once whenever a signal in the sensitivity list changes value begin if (sel) out = a; Statements within the always else out = b; block are executed sequentially. Order matters outbar = out; Surround multiple statements in a end single always block with begin/end. endmodule L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 11„„„„„ Verilog Registers Verilog Registers In digital design, registers represent memory elements (we will study these in the next few lectures) Digital registers need a clock to operate and update their state on certain phase or edge Registers in Verilog should not be confused with hardware registers In Verilog, the term register (reg) simply means a variable that can hold a value Verilog registers don’t need a clock and don’t need to be driven like a net. Values of registers can be changed anytime in a simulation by assuming a new value to the register L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 12„„ Mix-and-Match Assignments Mix-and-Match Assignments Procedural and continuous assignments can (and often do) co-exist within a module Procedural assignments update the value of reg. The value will remain unchanged till another procedural assignment updates the variable. This is the main difference with continuous assignments in which the right hand expression is constantly placed on the left-side module mux_2_to_1(a, b, out, 1 a outbar, sel); out input a, b, sel; output out, outbar; b 0 outbar reg out; sel always (a or b or sel) begin procedural if (sel) out = a; else out = b; description end continuous assign outbar = out; description endmodule L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 13„„ The case Statement The case Statement case and if may be used interchangeably to implement conditional execution within always blocks case is easier to read than a long string of if...else statements module mux_2_to_1(a, b, out, module mux_2_to_1(a, b, out, outbar, sel); outbar, sel); input a, b, sel; input a, b, sel; output out, outbar; output out, outbar; reg out; reg out; always (a or b or sel) always (a or b or sel) begin begin if (sel) out = a; case (sel) else out = b; 1’b1: out = a; end 1’b0: out = b; endcase assign outbar = out; end endmodule assign outbar = out; endmodule Note: Number specification notation: size’basenumber (4’b1010 if a 4-bit binary value, 16’h6cda is a 16 bit hex number, and 8’d40 is an 8-bit decimal value) L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 14„„ The Power of Verilog: n-bit Signals The Power of Verilog: n-bit Signals Multi-bit signals and buses are easy in Verilog. 2-to-1 multiplexer with 8-bit operands: module mux_2_to_1(a, b, out, outbar, sel); input7:0 a, b; 8 input sel; 1 a output7:0 out, outbar; 8 reg7:0 out; out always (a or b or sel) b 0 outbar begin 8 8 if (sel) out = a; sel else out = b; end assign outbar = out; endmodule Concatenate signals using the operator assign b7:0,b15:8 = a15:8,a7:0; effects a byte swap L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 15„„ The Power of Verilog: Integer Arithmetic The Power of Verilog: Integer Arithmetic Verilog’s built-in arithmetic makes a 32-bit adder easy: module add32(a, b, sum); input31:0 a,b; output31:0 sum; assign sum = a + b; endmodule A 32-bit adder with carry-in and carry-out: module add32_carry(a, b, cin, sum, cout); input31:0 a,b; input cin; output31:0 sum; output cout; assign cout, sum = a + b + cin; endmodule L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 16Dangers of Verilog: Incomplete Specification Dangers of Verilog: Incomplete Specification Goal: Proposed Verilog Code: module maybe_mux_3to1(a, b, c, sel, out); input 1:0 sel; a input a,b,c; 00 output out; b out 01 reg out; c 10 always (a or b or c or sel) begin 2 case (sel) sel 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; 3-to-1 MUX endcase (‘11’ input is a don’t-care) end endmodule Is this a 3-to-1 multiplexer? L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 17„„ Incomplete Specification Infers Latches Incomplete Specification Infers Latches Synthesized Result: module maybe_mux_3to1(a, b, c, sel, out); input 1:0 sel; input a,b,c; output out; a 00 reg out; b DQ out 01 always (a or b or c or sel) c begin 10 G case (sel) 2'b00: out = a; 2 2'b01: out = b; sel 2'b10: out = c; endcase sel1 end endmodule sel0 if out is not assigned Latch memory “latches” during any pass through old data when G=0 (we will discuss latches later) the always block, then the previous value must be In practice, we almost never intend this retained L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 18†† „ „ Avoiding Incomplete Specification Avoiding Incomplete Specification always (a or b or c or sel) begin out = 1’bx; Precede all conditionals case (sel) with a default assignment 2'b00: out = a; for all signals assigned 2'b01: out = b; 2'b10: out = c; within them… endcase end endmodule always (a or b or c or sel) …or, fully specify all begin case (sel) branches of conditionals and 2'b00: out = a; assign all signals from all 2'b01: out = b; branches 2'b10: out = c; default: out = 1’bx; For each if, include else endcase end For each case, include default endmodule L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 19Dangers of Verilog: Priority Logic Dangers of Verilog: Priority Logic Goal: Proposed Verilog Code: 4-to-2 Binary Encoder module binary_encoder(i, e); input 3:0 i; output 1:0 e; 0 I 3 reg e; I E 1 1 2 1 I E 0 0 1 0 always (i) I begin 0 0 if (i0) e = 2’b00; else if (i1) e = 2’b01; I I I I E E else if (i2) e = 2’b10; 3 2 1 0 1 0 else if (i3) e = 2’b11; 0 0 0 1 0 0 else e = 2’bxx; 0 0 1 0 0 1 end 0 1 0 0 1 0 endmodule 1 0 0 0 1 1 all others X X What is the resulting circuit? L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 20„ Priority Logic Priority Logic Code: if i0 is 1, the result is 00 Intent: if more than one input is 1, the result is a don’t-care. regardless of the other inputs. i0 takes the highest priority. I I I I E E 3 2 1 0 1 0 if (i0) e = 2’b00; 0 0 0 1 0 0 else if (i1) e = 2’b01; 0 0 1 0 0 1 else if (i2) e = 2’b10; 0 1 0 0 1 0 else if (i3) e = 2’b11; 1 0 0 0 1 1 else e = 2’bxx; end all others X X Inferred 2’b11 2’b10 2’b01 2’b00 1 1 1 1 Result: e1:0 2’bxx 0 0 0 0 i3 i2 i1 i0 if-else and case statements are interpreted very literally Beware of unintended priority logic. L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 21†† „ Avoiding (Unintended) Priority Logic Avoiding (Unintended) Priority Logic Make sure that if-else and case statements are parallel If mutually exclusive conditions are chosen for each branch... ...then synthesis tool can generate a simpler circuit that evaluates the branches in parallel Parallel Code: Minimized Result: module binary_encoder(i, e); input 3:0 i; output 1:0 e; I 3 reg e; E 0 always (i) I begin 1 E if (i == 4’b0001) e = 2’b00; 1 I 0 else if (i == 4’b0010) e = 2’b01; else if (i == 4’b0100) e = 2’b10; else if (i == 4’b1000) e = 2’b11; else e = 2’bxx; end endmodule L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 22„„„ Interconnecting Modules Interconnecting Modules Modularity is essential to the success of large designs A Verilogmodule may contain submodules that are “wired together” High-level primitives enable direct synthesis of behavioral descriptions (functions such as additions, subtractions, shifts ( and ), etc. Example: A 32-bit ALU Function Table A31:0 B31:0 F2 F1 F0 Function 0 0 0 A + B 32’d1 32’d1 0 0 1 A + 1 F0 01 01 0 1 0 A - B F2:0 0 1 1 A - 1 + - 1 0 X A B 00 01 10 F2:1 R31:0 L3: 6.111 Spring 2006 Introductory Digital Systems Laboratory 23

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