characteristics of logic families ppt

delay analysis methods and cmos circuit and logic design
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Dr.ShawnPitt,Netherlands,Teacher
Published Date:25-07-2017
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Performance Characterization • Delay analysis • Transistor sizing • Logical effort • Power analysis James Morizio ECE 261 1Delay Definitions • t : rising propagation delay pdr – From input to rising output crossing V /2 DD • t : falling propagation delay pdf – From input to falling output crossing V /2 DD • t : average propagation delay pd – t = (t + t )/2 pd pdr pdf • t : rise time r – From output crossing 0.2 V to 0.8 V DD DD • t : fall time f – From output crossing 0.8 V to 0.2 V DD DD James Morizio ECE 261 2Simulated Inverter Delay • Solving differential equations by hand is too hard • SPICE simulator solves the equations numerically – Uses more accurate I-V models too • But simulations take time to write 2.0 1.5 1.0 (V) t = 66ps t = 83ps pdf pdr V in V out 0.5 0.0 0.0 200p 400p 600p 800p 1n t(s) James Morizio ECE 261 3Delay Estimation • We would like to be able to easily estimate delay – Not as accurate as simulation – But easier to ask “What if?” st • The step response usually looks like a 1 order RC response with a decaying exponential. • Use RC delay models to estimate delay – C = total capacitance on output node – Use effective resistance R = RC – So that t pd • Characterize transistors by finding their effective R – Depends on average current as gate switches James Morizio ECE 261 4RC Delay Models • Use equivalent circuits for MOS transistors – Ideal switch + capacitance and ON resistance – Unit nMOS has resistance R, capacitance C – Unit pMOS has resistance 2R, capacitance C • Capacitance proportional to width • Resistance inversely proportional to width d s kC kC R/k 2R/k d d kC g k g g k g s kC kC s kC s d James Morizio ECE 261 5Example: 3-input NAND • Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). James Morizio ECE 261 6Example: 3-input NAND • Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). James Morizio ECE 261 7Example: 3-input NAND • Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 2 2 2 3 3 3 James Morizio ECE 261 83-input NAND Caps • Annotate the 3-input NAND gate with gate and diffusion capacitance. 2 2 2 3 3 3 James Morizio ECE 261 93-input NAND Caps • Annotate the 3-input NAND gate with gate and diffusion capacitance. 2C 2C 2C 2C 2C 2C 2 2 2 2C 2C 2C 3C 3 3C 3C 3 3C 3C 3 3C 3C James Morizio ECE 261 103-input NAND Caps • Annotate the 3-input NAND gate with gate and diffusion capacitance. 2 2 2 9C 3 5C 3C 3 5C 3C 3 5C James Morizio ECE 261 11Elmore Delay • ON transistors look like resistors • Pullup or pulldown network modeled as RC ladder • Elmore delay of RC ladder t » R C  pd i-to-source i nodes i = R C + R + R C + ... + R + R + ... + R C ( ) ( ) 1 1 1 2 2 1 2 N N R R R R 1 2 3 N C C C C 1 2 3 N James Morizio ECE 261 12Example: 2-input NAND • Estimate worst-case rising and falling delay of 2- input NAND driving h identical gates. 2 2 Y A 2 h copies x 2 B James Morizio ECE 261 13Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. 2 2 Y 4hC 6C A 2 h copies x 2C 2 B James Morizio ECE 261 14Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. 2 2 Y 4hC 6C A 2 h copies x 2C 2 B R Y t = pdr (6+4h)C James Morizio ECE 261 15Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. 2 2 Y 4hC 6C A 2 x 2C h copies 2 B R Y t = 6 + 4h RC ( ) pdr (6+4h)C James Morizio ECE 261 16Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. 2 2 Y 4hC 6C A 2 h copies x 2C 2 B James Morizio ECE 261 17Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. 2 2 Y 4hC 6C h copies A 2 x 2C 2 B R/2 x Y t = 2C (6+4h)C pdf R/2 James Morizio ECE 261 18Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. 2 2 Y 4hC 6C A 2 h copies x 2C 2 B R R R t = 2C + 6 + 4h C +   ( ) ( ) ( ) ( ) R/2 pdf 2 2 2   x Y 2C (6+4h)C R/2 = 7 + 4h RC ( ) James Morizio ECE 261 19Delay Components • Delay has two parts – Parasitic delay • 6 or 7 RC • Independent of load – Effort delay • 4h RC • Proportional to load capacitance James Morizio ECE 261 20

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