MOS transistor theory ppt

mos transistor principle ppt and mos field effect transistor ppt
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Dr.ShawnPitt,Netherlands,Teacher
Published Date:25-07-2017
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MOS Transistors Width W Gate Length SiO (insulator) Gate 2 L Drain Source Drain Source nMOS transistor n n channel Gate p-type (doped) substrate Conductor (poly) Drain Source pMOS transistor • Silicon substrate doped with impurities • Adding or cutting away insulating glass (SiO ) 2 • Adding wires made of polycrystalline silicon (polysilicon, poly) or metal, insulated from the substrate by SiO 2 James Morizio EE 261 1Silicon Lattice • Transistors are built on a silicon substrate • Silicon is a Group IV material • Forms crystal lattice with bonds to four neighbors Si Si Si Si Si Si Si Si Si James Morizio EE 261 2Dopants • Silicon is a semiconductor • Pure silicon has no free carriers and conducts poorly • Adding dopants increases the conductivity • Group V: extra electron (n-type) • Group III: missing electron, called hole (p-type) Si Si Si Si Si Si - + + - Si As Si Si B Si Si Si Si Si Si Si James Morizio EE 261 3p-n Junctions • A junction between p-type and n-type semiconductor forms a diode. • Current flows only in one direction p-type n-type anode cathode James Morizio EE 261 4nMOS Transistor • Four terminals: gate, source, drain, body • Gate – oxide – body stack looks like a capacitor – Gate and body are conductors – SiO (oxide) is a very good insulator 2 – Called metal – oxide – semiconductor (MOS) capacitor Source Gate Drain – Even though gate is Polysilicon SiO no longer made of metal 2 n+ n+ p bulk Si James Morizio EE 261 5nMOS Operation • Body is commonly tied to ground (0 V) • When the gate is at a low voltage: – P-type body is at low voltage – Source-body and drain-body diodes are OFF – No current flows, transistor is OFF Source Gate Drain Polysilicon SiO 2 0 n+ n+ S D p bulk Si James Morizio EE 261 6nMOS Operation Cont. • When the gate is at a high voltage: – Positive charge on gate of MOS capacitor – Negative charge attracted to body – Inverts a channel under gate to n-type – Now current can flow through n-type silicon from source through channel to drain, transistor is ON Source Gate Drain Polysilicon SiO 2 1 n+ n+ S D p bulk Si James Morizio EE 261 7pMOS Transistor • Similar, but doping and voltages reversed – Body tied to high voltage (V ) DD – Gate low: transistor ON – Gate high: transistor OFF – Bubble indicates inverted behavior Source Gate Drain Polysilicon SiO 2 p+ p+ n bulk Si James Morizio EE 261 8Power Supply Voltage • GND = 0 V • In 1980’s, V = 5V DD • V has decreased in modern processes DD – High V would damage modern tiny transistors DD – Lower V saves power DD • V = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, … DD James Morizio EE 261 9Transistors as Switches • We can view MOS transistors as electrically controlled switches • Voltage at gate controls path from source to drain g = 0 g = 1 d d d OFF nMOS g ON s s s d d d OFF pMOS g ON s s s James Morizio EE 261 10MOS Transistor Switches a a N-switch S = 0 0 0 s s N S = 1 b (degraded) 1 1 b Good 0, Poor 1 James Morizio EE 261 11MOS Transistor Switches a P-switch a S = 1 1 1 s P s (degraded) S = 0 0 0 b Good 1, Poor 0 b CMOS switch s s (Transmission s gate) a S = 0 b a a C b b Good 0 S = 1 s Good 1 s James Morizio EE 261 12Signal Strength • Strength of signal – How close it approximates ideal voltage source • V and GND rails are strongest 1 and 0 DD • nMOS pass strong 0 – But degraded or weak 1 • pMOS pass strong 1 – But degraded or weak 0 • Thus nMOS are best for pull-down network James Morizio EE 261 13CMOS Inverter A Y V DD 0 1 A Y A Y GND James Morizio EE 261 14CMOS Logic Gates-1 V Inverter DD Pull-up path Pull-down Pull-up Input truth table truth table Output a a a b z a b z Pull-down 0 0 1 path 0 0 Z 0 1 1 0 1 Z Gnd 1 0 1 1 0 Z V DD 1 1 Z 1 1 0 Pull-up tree NAND 2-input NAND a truth table b a b z z 0 0 1 a Pull-down 0 1 1 tree 1 0 1 b 1 1 0 Gnd James Morizio EE 261 15CMOS Inverter A Y V DD 0 OFF 1 0 A=1 Y=0 ON A Y GND James Morizio EE 261 16CMOS Inverter A Y V DD 0 1 ON 1 0 A=0 Y=1 OFF A Y GND James Morizio EE 261 17CMOS NAND Gate A B Y 0 0 Y 0 1 1 0 A 1 1 B James Morizio EE 261 18CMOS NAND Gate A B Y ON ON 0 0 1 Y=1 0 1 A=0 OFF 1 0 1 1 B=0 OFF James Morizio EE 261 19CMOS NAND Gate A B Y ON OFF 0 0 1 Y=1 0 1 1 A=0 OFF 1 0 1 1 B=1 ON James Morizio EE 261 20

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