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Holographic Information Systems Thesis by George Panotopoulos In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy California Institute of Technology Pasadena, California 2003 (Defended July, 2002)Abstract The goal of this work is to investigate the use of holographic techniques for infor- mation processing and transmission systems. Until recently information has been processed and transmitted mainly electronically. With the advent of optical fiber communications the monopoly of electronics has receded in the telecommunica- tions field, but the domain of information processing is still dominated by electronic processors. This thesis follows a top-down approach to the design of processors that integrate both electronic and optical components. It begins with the design considerations of a compact, rapidly reconfigurable opto-electronic processor, which possesses an optical bus in addition to the traditional electronic bus. The optical bus takes advan- tage of the massive parallelism that is afforded by optics and can be coupled to a holographic digital memory, allowing rapid reconfiguration of the device. The capa- bility of rapid reconfiguration gives rise to a new computational paradigm, where the reprogramming of the device can become part of the computation. We suggest additional applications of this processor, namely as a smart reading head for large scale holographic disk memories. Finally we present novel algorithms that were developed specifically to take advantage of the additional capabilities of our pro- cessor. The next section is concerned with the wavelength and angular tuning of strong volume holograms, both in the reflection and 90-degree geometries. Since photons have no charge, we need to rely on their wave properties to manipulate them, both for long-range transmission, such as telecommunications, and short-range trans- mission, such as on chip interconnects. In this section we investigate how volume holograms can be used to selectively redirect information bearing light beams. The final part of this thesis is concerned with material issues. Holographic record- ing of strong volume gratings is one of the most commonly used approaches, and photorefractive materials have a strong bearing on the overall performance of the final system. Two properties of iron doped lithium niobate are investigated, namely vithe dependence of absorption on temperature and the quadratic electro-optic coef- ficient. The former is crucial for the commonly used technique of thermal fixing, and the latter can become significant should we choose to use applied continuous fields to tune our gratings. vii1 Introduction 1.1 Holography for information systems In this thesis we investigate the use of holography in the context of information pro- cessing. Information can be encoded on light beams, by modifying their temporal or spatial properties. Holograms can be used to manipulate the properties of those light beams, effectively processing the information they bear. In this section we will discuss, in the most general terms, what kind of processing can be implemented using holographic elements. Plane waves are the eigenmodes of free space 1-1. Sinusoidal gratings can be used to couple two such elementary modes 1-2. It is also possible to superimpose multiple gratings in the same volume, thus enabling more complicated wavefronts to be coupled to the input wavefront. In most holographic memory systems, a 1Introduction single reference plane wave is coupled to multiple gratings in order to reconstruct the highly structured information page 1-3. These memories can be interfaced to optoelectronic circuits, thus enhancing key aspects of their performance 1-4,1-5. Due to their large number of periods, holographic gratings exhibit significant selec- tivity to angular and wavelength detuning. It is, therefore, possible for strong volume holograms to act as filters that isolate and redirect specific spatial and spectral information. Such gratings can be used to implement tunable intercon- nects for a chip, act as wavelength filters 1-6,1-7 or demultiplexers 1-8 for Wave- length Division Multiplexing (WDM) fiber communications systems, or be used to perform spatially and spectrally selective imaging 1-9,1-10. In this thesis we will focus on the investigation of two of these possible uses. The first is the use of holograms as memory elements, and their combination with opto- electronic circuits. The second is the use of strong holographic volume gratings as filtering elements for WDM optical communications. In the next sections of this chapter we present an outline of the thesis. 1.2 Optically programmable gate arrays We will begin in Chapter 2 by detailing the design, implementation, and testing of a compact, rapidly reconfigurable, optoelectronic processor. We will go through ini- tial design considerations and briefly mention all the constituent components, spending more time on the testing and integration of the silicon circuit that com- bines photodetectors with logic circuits. We will then detail experiments to imple- ment and test the integration of these devices, culminating in the demonstration of holographic reconfiguration of our processor. In Chapter 3, we will generalize our architecture, and show how a real-time video processing algorithm can be mapped to it. Then, we will present two algorithms specifically designed to take advantage of this device. The first one is a Neural Net- work based approach to the classification of cursive digits, that presents a new computational paradigm by introducing the reconfiguration of the device as part of the computation. The second one is an algorithm that allows OPGA’s to be used 2Introduction as smart head that are able to retrieve classes of objects from large, non indexed holographic databases. 1.3 Strong volume gratings As mentioned in Section 1.1, strong volume gratings can be used to implement tun- able interconnects as well as filters of WDM fiber communication systems. In Chapter 4 we will investigate the behavior of strong gratings, in the reflection geometry. We will start with a general treatment of waves in two-dimensional peri- odic media. Then we will focus on the reflection geometry, and investigate some of the finer aspects of the coupled mode theory, with applications to polarization dependence, angular, wavelength, and thermal detuning. Finishing with the reflec- tion geometry we present experimental results confirming our theories. We will then proceed to the 90-degree geometry, in Chapter 5. We will extend the coupled mode formalism to two dimensions, and present theoretical and experi- mental results regarding diffraction efficiency. Next, we will discuss wavelength detuning, and develop a numerical solution for the coupled-mode equations in that case. We will conclude the chapter with a numerical calculation of the impulse response of strong volume gratings in the 90-degree geometry. 1.4 Materials In Chapter 4 and Chapter 5, we discuss the use of strong volume gratings as filters. In this context the lifetime of the recorded gratings becomes an issue. One of the most promising methods to increase the lifetime of holographically recorded grat- ings is thermal fixing, which involves recording at elevated temperatures. In Chapter 6 we will discuss the effects of temperature on the absorption spectrum of iron doped lithium niobate (LiNbO ). First we will give an outline of the absorption 3 mechanisms. Then we will present the experimental methods we used and the results obtained. Finally we will propose a theoretical model that explains our experimental observations, and discuss its implications in terms of possible appli- cations and extensions to different dopants. 3Introduction Our ability to record gratings in photorefractive materials is due to the electro-optic effect, which allows electric fields induced by charge redistribution to be mani- fested as a modulation of the refractive index. Though the presence of grating is due, for all practical purposes, to the linear electro-optic effect, it is of interest to investigate the magnitude of the quadratic electro-optic effect. In Chapter 7 we will begin by reviewing an experimental setup used to measure the linear electro-optic coefficients. We will then proceed to describe the limitations that prevent the use of such a setup for the measurement of the quadratic electro-optic coefficients, highlighting the challenges presented. Finally, we will present the design of a mea- surement system capable of measuring the quadratic electro-optic coefficients, even in the presence of much stronger linear electro-optic coefficients, as well as results for the case of manganese-doped lithium niobate (LiNbO :Mn). 3 1.5 References 1-1 A. Yariv and P. Yeh, Optical Waves in Crystals. 1984, New York: John Wiley & Sons. 1-2 H. Kogelnik, Coupled Wave Theory for Thick Hologram Gratings. Bell System Technical Journal, 1969. 48(9): pp. 2909-2947. 1-3 H. J. Coufal, G. Sincerbox, and D. Psaltis, eds. Topics in Applied Physics: Holo- graphic Memories. 1999, Springer: Berlin, New York, Tokyo. 1-4 J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis. Opti- cally reconfigurable processors. in Euro-American Workshop on Optoelectronic Information Processing. 1999: SPIE. 1-5 J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum. Optically programmable gate array. in Proc. SPIE of Optics in Computing. 2000. 1-6 V. Leyva, G. A. Rakuljic, and B. O'Conner, Narrow bandwidth volume holo- graphic optical filter operating at the Kr transition at 1547.82 nm. Applied Physics Letters, 1994. 65(9): pp. 1079-1081. 4Introduction 1-7 J. Hukriede, I. Nee, D. Kip, and E. Kratzig, Thermally fixed reflection gratings for infrared light in LiNbO :Ti:Fe channel waveguides. Optics Letters, 1998. 23(17): 3 pp. 1405-1407. 1-8 S. Breer, H. Vogt, I. Nee, and K. Buse, Low-crosstalk WDM by Bragg diffraction from thermally fixed reflection holograms in lithium niobate. Electronics Letters, 1998. 34(25): pp. 2419-2421. 1-9 G. Barbastathis, M. Balberg., and D.J. Brady, Confocal microscopy with a volume holographic filter. Optics Letters, 1999. 24(12): pp. 811-813. 1-10 W. H. Liu, D. Psaltis, and G. Barbastathis, Real-time spectral imaging in three spa- tial dimensions. Optics Letters, 2002. 27(10): pp. 854-856. 52 Optically programmable gate array 2.1 Introduction Information processing and transmission has been dominated, until recently, by the use of electronic encoding. This is due to the fact that electrons, thanks to their charge, are fairly easy to manipulate, and since they constitute part of matter, it is straightforward to achieve interaction between a device and an electronic stream of information. In the last few years, optical and optoelectronic systems have been widely adopted in the realm of telecommunications, a trend mainly due to their higher bandwidth. Still, there is no similar penetration of use of optical techniques in local information processing. This is due to photons having no charge, thus forc- ing us to manipulate them by taking advantage of their wave properties. Neverthe- 6Optically programmable gate array less, it is considerably harder to force light to interact with matter than it is to force electrons to do so. On the other hand, again due to the lack of charge, photons have the very advan- tageous property of not interacting with each other. This inherently reduces the crosstalk of optical communications, and allows unprecedented degrees of paral- lelism in on-chip interconnects, hardly conceivable in the case of purely electronic circuits. Furthermore, the decrease of device size in VLSI circuits is not followed by a similar decrease in interconnect dimensions. As devices shrink and operating fre- quencies increase the need for more efficient, less real-estate-consuming intercon- nection solutions will become pressing. We believe that optical interconnects will provide an elegant solution to this problem 2-1. In this chapter, we propose the use of photonics to implement data transfer, on a chip scale. More specifically, we discuss the design, fabrication, and characteriza- tion of a compact, rapidly reconfigurable optoelectronic processor 2-3, 2-4, which relies on the interfacing of a silicon optoelectronic circuit with a holographic optical memory 2-5, 2-6. The device we propose is an extension of a Field Programma- ble Gate Array (FPGA) 2-7, a widely used class of reconfigurable digital circuits. The main idea behind FPGA’s is that any Boolean function can be implemented by proper combination of elementary Boolean functions (e.g., all Boolean functions can be implemented using NAND gates). FPGA circuits contain two components: • Reconfigurable look-up tables (LUT’s). • Reconfigurable interconnects. The LUT’s implement elementary Boolean functions. By configuring the look-up tables and combining their outputs using interconnects, FPGA’s can implement any logic function. The versatility, ease of programming, and computing power of FPGA’s has propelled them from limited use in development and prototyping, which was their initial target application, to widespread use in many commercial electronic products. In addition, FPGA’s, occupying the middle ground between the processing power of Application Specific Integrated Circuits (ASIC’s) and the ease 7Optically programmable gate array of programming of microprocessors, are widely used in demanding Digital Signal Processing (DSP) applications 2-8, 2-9. The enhancement of FPGA’s with optical interfaces has been discussed in litera- ture, mainly in terms of high-bandwidth I/O 2-10 and interchip interconnects 2- 11. The device we propose, namely the Optically Programmable Gate Array (OGPA), addresses one of the main limitations of FPGA’s: Their long reconfigura- tion time. FPGA’s have only one set of inputs/outputs (I/O), they communicate electronically through the pins of the chip. Since most of these I/O resources are used for the transfer of data that is processed by the device, very few I/O ports are available for its reconfiguration. As a result the reconfiguration of an FPGA can last several milliseconds, and in practice FPGA’s are programmed before the data pro- cessing begins and do not alter their functionality during operation. By contrast, the OPGA has an additional set of inputs, namely a set of photodetec- tors on the surface of the chip. These inputs are linked to a holographic memory that contains the reconfiguration data necessary to program the logic functionality of the device. The inherent 2-D aspect of holographic memories, combined with fast access, allows OPGA’s to be reprogrammed in a matter of microseconds, thus providing a new computational paradigm, where the reconfiguration of the device can be part of the computation. In this chapter we discuss the design and implementation of the OGPA device. We present the elements of the device and some of the trade-offs involved. Then we focus on the chip that combines the reconfigurable logic and detectors, discuss the methods used to characterize it and the corresponding results. Finally, we intro- duce a demo setup that showcases the successful reconfiguration of an electronic circuit, using a holographic memory. 2.2 Elements of the OPGA The OPGA is composed of the following basic elements (see Figure 2-1): • A silicon integrated circuit combining reconfigurable logic and photodetectors. 8Optically programmable gate array Figure 2-1. Compact OPGA module. The addressing devices access different pages stored in the holographic memory element. The information contained in these pages is imaged on the surface of the chip. There photodetectors collect the information, which is then used to reconfigure the programmable logic that is also implemented on the chip. • A holographic memory element, where the reconfiguration templates are stored. • An addressing device, used to access information in the holographic memory, and transfer it to the silicon circuit. The processing element of the OGPA is located on the silicon circuit, and is imple- mented by configuring properly the logic blocks and interconnects. The information required to configure the processing element is stored in the holographic memory element. When we want to change the functionality of the processing element we use an addressing device to select a specific reconfiguration data page from the memory, and transfer it on the surface of the chip. There, the photodetectors receive this information, which is then routed to the reconfigurable elements. The information is used to change the parameters of these elements, leading to the implementation of a new functionality. The holographic memory element can be made using several different materials, such as polymers (Aprilis 2-12, DuPont 2-13), or photorefractive crystals (LiNbO :Fe), and the information can be recorded using a number of different mul- 3 tiplexing techniques, such as reflection geometry 2-14, transmission geometry, o 90 geometry 2-15, shift multiplexing 2-16, and peristrophic multiplexing 2-17. In selecting the holographic material and multiplexing technique, we need to address the competing needs for memory capacity and efficient reconstruction of the stored information 2-18. 916x2 Pi 16x2 Pixel xel Ar Array ray Optically programmable gate array The addressing devices are crucial in determining the minimum reconfiguration time, in the sense that they should enable us to access rapidly different memory pages, and have enough power, so that the information that is reconstructed on the surface of the chip can be integrated by the photodetectors in a short time. Devices that fulfill these requirements are arrays of Vertical Cavity Surface Emitting Lasers (VCSEL’s) 2-19, and Micro-electro-mechanical (MEM’s) arrays combined with laser diodes. 2.3 The OGPA chip The OPGA chip consists of two main elements: a photodetector array and recon- figurable logic. Since the reconfiguration data is to be transferred from the memory to the photodetectors, and then to be used to reconfigure the LUT’s and intercon- nects, it would make sense to place the reconfigurable logic elements and the pho- todetectors used to reconfigure them in close proximity. Such an optically Ou Outp tput ut Latch Latch Latch Latch Latch Latch Latch Latch Latch Latch Latch Latch X1 X1 Latch Latch Latch Latch Latch Latch Latch Latch Latch X2 X2 Latch Latch Latch Latch Latch Latch Latch Latch Latch X3 X3 Latch Latch Latch Latch Latch Latch X4 X4 Latch Latch Latch Latch Latch Latch Latch Latch Latch Latch Latch Latch Figure 2-2. Optically Reconfigurable Look-Up Table. The information received by the photodetector array is stored in the latches. The input defines through a decoder which latch value will be output, thus implementing the LUT. reconfigurable LUT is shown in Figure 2-2. Optical information collected by the Active Pixel Sensor (APS) array is transferred to an array of 16 latches. A four-bit 10 4-bit Decoder 4-bit DecoderOptically programmable gate array decoder receives an input and presents the contents of the corresponding latch at the output. By selecting the values stored in the latches we can implement any 4- bit input, 1-bit output Boolean function. Combining the photodetectors and reconfigurable logic elements has obvious advantages, in terms of minimizing the wiring required for configuration-data trans- fer. On the other hand, such a design results in bigger pixels with smaller fill-factor, putting a strain on the power requirements of the laser source, and the diffraction efficiency requirements of the holographic memory. We designed and fabricated a prototype OPGA chip in collaboration with Photobit Inc. The chip was fabricated using a 0.35 micron, CMOS technology. It is shown in Figure 2-3, where the two main elements, the photodetector array and the recon- figurable logic, are easily distinguishable. In this prototype chip we chose to imple- Figure 2-3. Photograph of the OPGA chip. (a) 64 × 64 Active Pixel Sensor Array. (b) Reconfigurable logic. ment the photodetector array and the logic at different locations, mainly in order to facilitate testing. The trade-offs between the two possible designs should be con- 11Optically programmable gate array sidered in future implementations. In the following sections we describe in detail these two elements. 2.3.1 The APS array The photodetector array was implemented as a 64 × 64 active pixel sensor differ- ential array 2-20, 2-21. Each pixel of this array is an active pixel, the difference V V V V V V V V V DD DD DD DD DD DD DD DD DD Re Re Res s se e et t t Re Re Res s se e ettt F F Fllloati oati oatin n ng g g F F Fllloati oati oatin n ng g g Pi Pi Pix x xe e elll Output Output Output Di Di Diffffffu u us s siiio o on n n Di Di Diffffffu u us s siiio o on n n R R Read ead ead R R Read ead ead Pi Pi Pix x xe e elll O O Ou u utput tput tput Passive Pixel Passive Pixel A Active Pixel ctive Pixel Figure 2-4. Schematic diagrams of Passive and Active Pixels. For the Passive Pixel the charge of the floating diffusion is output directly. For the Active Pixel it is amplified in-situ before being output. between a passive pixel and an active pixel being that in an active pixel the charge generated by the photodiode is actively amplified before being red-out (see Figure 2-4). As a result, active pixels achieve significantly better signal-to-noise (SNR) ratios than their passive counterparts. The array also employs differential encoding, so that every pair of pixels encodes only one bit, i.e., a pixel combination of dark-bright corresponds to 1 and a combi- nation of bright-dark corresponds to 0. This encoding is a rudimentary error correct- ing code, used to counter the fact that the intensity across large reconstructed holographic data pages is not constant. The pixel combinations dark-dark and bright-bright are not permitted, and result to a random flickering value and a zero value respectively. Examples illustrating the concept of differential encoding are shown in Figure 2-5. The differential encoding is implemented by driving the output voltages of the two pixels of a pixel pair through a comparator, as shown in 12Optically programmable gate array Figure 2-5. Examples of differential encoding. The left column corresponds to the data projected on the APS array, with white squares corresponding to illuminated pixels and black ones to dark pixels. The right column corresponds to the data that is read out, with black corresponding to 1 and white corresponding to 0. The last two examples illustrate the response of the array to nondifferential inputs. Figure 2-6. The nonpermitted states result from the fact that the corresponding inputs drive the comparator out of its normal operation region. The different behav- ior for different nonpermitted states stems from the asymmetric design of the com- parator. The APS array can be read row-wise, and rows can be accessed in random order. When a row is being read out, the corresponding pixel values are compared pair- 13Optically programmable gate array Reset SEL i WR RD A Left + D Pixel CMP Q - A D Right Reset Pixel Reset Pixel Latch Output Bus Bus Bus Figure 2-6. Schematic diagram of the differential APS pair. The two pixels are amplified independently, and then driven through a comparator. The outcome of the comparison is stored in a latch, and accessed during readout. wise, and the resulting outcomes are stored at the output latches of the array. Due to differential encoding, the 64 × 64 APS array produces 64 lines of 32 bits. 2.3.2 The reconfigurable logic The reconfigurable logic, illustrated in Figure 2-7, consists of the following: Figure 2-7. Schematic diagram of the reconfigurable logic. It is composed from four 5-bit input, 1- bit output LUT’s, five interconnection matrixes and four I/O ports. 14Optically programmable gate array • Four 5-bit input, 1-bit output LUT’s. • Five interconnection matrixes. • Four I/O ports. • A five-line bus is used to transmit data to and from the different elements. Each input of each LUT can be connected to any bus line, and the same holds for 5 its output. Therefore the reconfiguration of a LUT block requires 2 = 32 bits for the LUT itself, 5 × 5 bits for the reconfiguration of the input connections, and 5 bits for the reconfiguration of the output connections, bringing the total to 62 bits. As a result two lines of the APS array are necessary to reconfigure any LUT block. Each of the five interconnection matrixes connects four segments of the 5-line bus. The corresponding lines of the four segments can be connected in 6 different ways, therefore 5×6 bits are required for the reconfiguration of an interconnection matrix, corresponding to a single line of the APS array. The I/O ports are implemented using tri-state buffers, so that they can be set to operate in input-only, output-only, or input-output mode. The reconfiguration of the entire logic requires 4×2 + 5×1 = 13 lines of the APS array. Since each data page consists of 64 lines, it contains enough information for four complete reconfigurations of the logic. 2.3.3 Performance characterization of the APS array The first test we performed on the chip was to characterize the APS array. The chip is mounted on a board that generates the necessary bias voltages and timing sig- nals. It also has an interface to the parallel port of a PC, through which we are able to collect and visualize the information displayed on the APS array. In order to test the APS array we need to pixel-match it to a Spatial Light Modulator (SLM), a liquid crystal device commonly used in overhead digital projectors. The pixel pitch of the APS array was designed to be 15 µm, equal to the pixel pitch of the Kopin 320 CyberDisplay SLM. There are several well-known techniques used to pixel-match SLM’s to detectors. They rely on the display of known geometrical patterns on the SLM, and subsequent adjustment of the detector’s position, based on the readout. 15Optically programmable gate array In the case of the APS array, the use of such a technique was rendered impossible due to the differential encoding used. Due to that, the output of the array flickers randomly when it is not pixel matched, and only stabilizes when we are very close to pixel match. In order to circumvent this hurdle we designed the optical setup shown in Figure 2-8. (a) (b) Figure 2-8. Pixel matching experimental setup. (a) Schematic diagram. (b) Detail of the experimental setup. In this setup the light of a HeNe laser is collimated and spatially modulated using the SLM. It is then imaged on the surface of the chip using a 4-f system, formed by 16Optically programmable gate array two low-aberration Nikon lenses. The chip and board are mounted on a combina- tion of translation and rotation stages allowing five degrees of freedom (three trans- lational and two rotational). The surface of the chip acts as a partial reflector, so the illuminating pattern is reflected back through the 4-f system. A beam-splitter, placed between the SLM and the first lens, splits the reflected light, part of which is imaged on a CCD camera through a microscope objective. A pair of LED’s illu- minates the surface of the chip independently, so that the image of the chip is superimposed to the image of the illuminating pattern on the CCD. Using the rota- tion and translation controls of the chip mount we are able to align the APS pixels and the illuminating pattern, thus achieving pixel-matching between the two, as shown in Figure 2-9. Figure 2-9. Images used for pixel matching. (a) Image of pixels. (b) Image of illumination pattern. (c) Superposition of pixels and illumination pattern. The next step is to vary the intensity of known illuminating patterns using a variable attenuator, and measure the number of errors on the APS output. We used both random and structured patterns, shown in Figure 2-10. More information about the patterns can be found in Table 2-1. The probability of error P is plotted vs. inten- e sity (arbitrary units) in Figure 2-11, for three different random patterns. The three patterns are generated using the same distribution of random numbers by chang- ing a threshold. Very low intensities lead essentially to the dark-dark combination 17