Digital logic design lab manual

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Texas A&M University Department of Electrical Engineering ELEN 248 Introduction to Digital Design Laboratory Manual Prepared and Revised by Daryl Reynolds David Rigsby Prof. Ray Mercer Lifford McLauchlan Dec. 2004CONTENTS ELEN 248 Laboratory Policies and Report Format 1 Lab 1: Introduction to Combinational Design 3 1.1 Introduction 1.2 Background 1.3 Prelab 1.4 Lab Procedure 1.4.1 Experiment 1 1.4.2 Experiment 2 1.4.3 Experiment 3 1.4.4 Experiment 4 1.4.5 Experiment 5 1.5 Post lab Lab 2: Introduction to Max+Plus II 11 2.1 Introduction 2.2 Background 2.3 Prelab 2.4 Lab Procedure 2.4.1 Experiment 1 2.4.2 Experiment 2 2.4.3 Experiment 3 2.4.4 Experiment 4 2.5 Postlab Lab 3: Adders 17 3.1 Introduction 3.2 Background 3.3 Prelab 3.3.1 Design 1 3.3.2 Design 2 3.3.3 Design 3 3.3.4 Questions 3.4 Lab Procedure 3.4.1 Experiment 1 3.4.2 Experiment 2 3.4.3 Experiment 3 3.4.4 Experiment 4 3.5 Postlab Lab 4: Signed Numbers 21 4.1 Introduction 4.2 Background 4.2.1 Two’s Complement Numbers 4.2.2 Signed Integer Arithmetic 4.3 Prelab 4.3.1 Design 1: Negation (Two’s Complement) 4.3.2 Design 2: Signed Integer Adder 4.3.3 Design 3: Signed Integer Subtracter 4.3.4 Questions 4.4 Lab Procedure 4.4.1 Experiment 1 4.4.2 Experiment 2 4.4.3 Experiment 3 4.5 Postlab Lab 5: 8-bit Counter with Debounced and Non-debounced Clock 26 5.1 Introduction 5.2 Background 5.2.1 The 8count 8-bit counter 5.2.2 Clock bounce 5.2.3 The SR latch 5.2.4 The seven segment display 5.3 Prelab 5.3.1 Design 1 5.3.2 Design 2 5.3.3 Design 3 5.3.4 Questions 5.4 Lab Procedure 5.4.1 Experiment 1 5.4.2 Experiment 2 5.5 Postlab Lab 6: 4-bit Shift Adder 32 6.1 Introduction 6.2 Background 6.2.1 The 74179 shift register 6.2.2 Binary addition via shifting 6.3 Prelab 6.3.1 Design 1 6.3.2 Design 2 6.3.3 Questions 6.4 Lab Procedure 6.4.1 Experiment 1 6.4.2 Experiment 2 6.5 Postlab Lab 7: 4-bit Shift Multiplier 36 7.1 Introduction 7.2 Background 7.2.1 The Altera internal clock and the clock divider circuit 7.2.2 4-bit shift multiplication 7.2.3 How to do it 7.3 Prelab 7.3.1 Design 1 7.3.2 Design 2 7.3.3 Questions 7.4 Lab Procedure 7.4.1 Experiment 1 7.4.2 Experiment 2 7.5 Postlab Lab 8: The Priority Encoder 41 8.1 Introduction 8.2 Background 8.3 Prelab 8.3.1 Design 1 8.3.2 Design 2 8.4 Lab Procedure 8.4.1 Experiment 1 8.4.2 Experiment 2 8.5 Postlab Lab 9: T-Bird Taillights 43 9.1 Introduction 9.2 Background 9.2.1 State Machines 9.2.2 T-bird Taillights9.3 Prelab 9.3.1 Design 1 9.3.2 Design 2 9.3.3 Design 3 9.3.4 Design 4 9.3.5 Questions 9.4 Lab Procedure 9.5 Postlab Lab 10: LED Pong 48 10.1 Introduction 10.2 Background 10.3 Prelab 10.3.1 Design 1 10.3.2 Design 2 10.3.3 Design 3 10.3.4 Design 4 10.4 Lab Procedure 10.5 PostlabELEN 248 Laboratory Manual, Policies and Report Format ELEN 248 Laboratory Policies and Report Format Reports are due at the beginning of the lab period. The reports are intended to be a compete documentation of the work done in preparation for and during the lab. The report should be complete so that someone else familiar with digital design could use it to verify your work. Portions of the prelab needed during lab should be duplicated before you arrive since the TA will collect the original. The prelab and postlab report format is as follows: 1. A neat thorough prelab must be presented to your lab instructor at (or before) the beginning of your scheduled lab period. Lab reports should be submitted on 8.5” x 11” paper, typed on one side only. Your report is a professional presentation of your work in the lab. Neatness, organization, and completeness will be rewarded. Points will be deducted for any part that is not clear. 2. Each report will contain the following sections: a) Cover Page: Include your name, ELEN 248, Section No., Lab No., TA’s name, and date b) Objectives: Enumerate 3 or 4 of the topics that you think the lab will teach you. DO NOT REPEAT the wording in the lab manual procedures. There should be one or two sentences per objective. Remember, you should write about what you will learn, not what you will do. These are not necessarily the same things. c) Design: This part contains all the steps required to arrive at your final circuit. This should include diagrams, tables, equations, K-maps, explanations, etc. Be sure to reproduce any tables you completed for the lab. This section should also include a clear written description of your design process. Simply including a circuit schematic is not sufficient. d) Schematics: As part of the design process for each lab (with the exception of the first two), you will create a gate-level schematic and turn it in with your report. The schematic must be complete. You should be able to copy it directly into Max+II and create a working circuit. Since the design process is completed before you come into lab, you may turn in a hand-drawn schematic, but it must be neatly drawn. Schematics that are difficult to read will receive no credit. e) Questions: Specific questions asked in the lab should be answered here. 1ELEN 248 Laboratory Manual, Policies and Report Format 3. Late prelabs will have 50% of the points deducted for being one day late. If a prelab is 2 days late, a grade of 0 will be assigned. The prelab for a two-week lab is due at the beginning of the first week’s lab period. 4. Your work must be original and prepared independently. However, if you need any guidance or have any questions or problems, please do not hesitate to call your Teaching Assistant (TA) during office hours. Copying any prelab will result in a grade of 0. The incident will be formally reported to the University. 5. Each laboratory exercise (circuit) must be completed and demonstrated to your TA before the prelab for the subsequent lab is due (1-2 weeks later) in order to receive working circuit credit. This is the procedure to follow: a) Circuit works: If the circuit works during the lab period (3 hours), call your TA, and he/she will sign and date it. You should then save your circuits on your own Zip disk before leaving the lab. This is the end of this lab, and you will get a complete grade (100) for this portion of the lab. b) Circuit does not work: If the circuit does not work, you must make use of the open times for the lab room (Zachry 115D) to complete your circuit. When your circuit is ready, contact your TA to set up a time when the two of you can meet to check your circuit. 6. You are guaranteed a computer and workspace in 115D Zachry only during your lab period. If you need to work on your circuits at a time other than your regularly scheduled lab period, the lab in 115D either is open or can be opened any time the instrument room is open (8 am - 9 pm M-F and 9 am - 5 pm Saturday). However, if another lab section is in progress, ask the TA if he/she has any open lab stations. 7. Attendance at your regularly scheduled lab period is required. An unexpected absence will result in loss of credit for your lab. Your lab instructor may permit rescheduling if you arrange for the change ahead of time. 2ELEN 248 Laboratory Manual, Lab 1 Lab 1: Introduction to Combinational Design 1.1 Introduction The purpose of this experiment is to introduce you to the basics of circuit wiring, troubleshooting, positive/negative logic, threshold voltages, clock, delay concepts, and gate behavior. In this lab, you will test the behavior of several of the basic logic gates and you will connect several logic gates together to create simple circuits. 1.2 Background None. 1.3 Prelab None. 1.4 Lab Procedure We will look at the behavior of some basic logic gates, including inverters, AND gates, OR gates, XOR gates, NAND gates, and NOR gates. Each of these gates is embedded in an integrated circuit package. See Figures 1.1 and 1.2 for pinouts for these circuits. More detailed specifications may be found in the TTL (Transistor-Transistor-Logic) book found in the instrument room (Zachry 111A). We will also investigate the concepts of positive and negative logic, threshold voltages, clock pulse, and delay. 1.4.1 Experiment 1 We will start by setting up the DC power supply and multimeter for our use. Be sure both are turned off. Then check to see that the multimeter is set to measure DC (button on far left), and be sure the red lead is connected to the red multimeter input that is marked for voltage (not current). Finally, set the scale to the 20V scale. Now, set the DC power supply voltage output to zero (turn the coarse adjustment counterclockwise until it stops). Connect the red lead of the power supply to the red lead of the multimeter. Likewise, connect the black lead of the power supply to the black lead of the multimeter. NOTE - DO NOT CONNECT POWER (RED) AND GROUND (BLACK) TOGETHER. This will cause a short. 3ELEN 248 Laboratory Manual, Lab 1 Fig. 1.1: Pinouts of the 7400 series TTL logic gates. 4ELEN 248 Laboratory Manual, Lab 1 Fig. 1.2: Pinouts of the 7400 series TTL logic gates. 5ELEN 248 Laboratory Manual, Lab 1 Turn on both the multimeter and the power supply. The multimeter should read very near zero. Turn the coarse adjustment clockwise until the multimeter reads 5V. If the multimeter display does not change significantly when you turn the coarse adjustment, turn the power supply off and recheck your connections. You may have a short. When the multimeter reads 5V, the adjustments are complete and you should turn off the power supply. You are ready to test your first gate. We will start by wiring a 74LS04 (inverter) gate. The pinouts for this chip may be found in Figure 1.1. Insert the 74LS04 chip onto the breadboard. Be sure you are not shorting pins together. Identify the power (VCC) and ground (GND) pins for the 74LS04. Connect the VCC pin to the red lead of the power supply and connect the GND pin to the black lead of the power supply (or multimeter). This chip (7404) contains 6 different inverter gates. Each inverter gate has an input pin and a corresponding output pin. Choose one of the gates and connect the red lead of the multimeter to the gate output. The black lead of the multimeter should always be connected to the black lead of the power supply (at the GND pin). Then connect a wire from either the VCC pin to the input (for a logic high input) or from the GND to the input (for a logic low input). Do not connect both at the same time, as this will cause a short. Turn on the power supply and observe the gate output. Assume A is the input to the inverter (either H or L) and that Y is the output. Fill in Table 1.1 according to the logic behavior that you observe. Note: First fill in the second column of the table using the readings from the multimeter. Then determine the answers to the last column based upon these readings. If the output is high (H), the multimeter will read approximately 4.4 volts; when it is low (L), the multimeter will read about 0.15 volts. If you read a voltage between these values, you have likely wired your circuit incorrectly. Tab. 1.1: Inverter logic behavior 1.4.2 Experiment 2 In a circuit, logic variables (values 0 and 1) can be represented as levels of voltage. The most obvious way of representing two logic values as voltage levels is to define a threshold voltage; any voltage below the threshold, represents one logic value and voltages above the threshold correspond to the other logic value. To implement the threshold – voltage concept, a range of low and high voltage levels is defined, as shown in Fig. 1.3. This figure indicates that voltages in the range Gnd to Vo,max represent logic value 0. Similarly, the range from V1,min to Vcc corresponds to logic value 1. Logic signals do not normally assume voltages in undefined range except in transition from one logic value to the other. 6ELEN 248 Laboratory Manual, Lab 1 Voltage Vcc Logic Value 1 V1,min Undefined V0,max Logic Value 0 Gnd Fig. 1.3: Representation of logic values by voltage levels Creating a variable input voltage from 0 to 5 volt, you will use a potential meter connected between Gnd and Vcc. Then connect its third pin (middle pin) to input of an inverter gate and measure its output voltage with the multimeter while the input voltage of the gate changes from 0 to 5 volt. Draw Vo–Vin curve for the inverter gate, what are the threshold values for high and low logic levels? Demonstrate the results to your TA. 1.4.3 Experiment 3 We are going to repeat the same experiment with the gates 74LS00 (NAND), 74LS02 (NOR), 74LS08 (AND), 74LS32 (OR), and 74LS86 (XOR). Note that each of the gates has two inputs and one output. Fill in Tables 1.2 and 1.3 to indicate the observed responses of these gates. So far we have reviewed the voltage behavior (H/L) of various gates. These devices will always behave according to the logic described in Tables 1.1-1.3. There is an abstract way to interpret this voltage behavior. We call this logic interpretation. Logic interpretation can be of two classes: positive or negative. The logic interpretation assigns logic levels (0 or 1) to the voltage inputs and outputs (H or L) of the devices. The levels are assigned according to Table 1.4. Use Table 1.4 to fill out Tables 1.5 and 1.6. Note that the tables should be filled with 0’s and 1’s, not H’s and L’s. If you still have questions, see your TA. Tab. 1.2: Basic gate logic behavior, part I 7ELEN 248 Laboratory Manual, Lab 1 Tab. 1.3: Basic gate logic behavior, part II Tab. 1.4: Logic Interpretation Tab. 1.5: Positive/Negative logic Tab. 1.6: Positive/Negative logic 1.4.4 Experiment 4 This experiment will introduce you to the procedures of wiring schematics. Connect the circuit in Figure 1.4 and complete logic behavior Table 1.7 using this circuit. Assume positive logic. Demonstrate this circuit to your teaching assistant. 8ELEN 248 Laboratory Manual, Lab 1 Fig. 1.4: Circuit A Tab. 1.7: Circuit A logic behavior 1.4.5 Experiment 5 This experiment will introduce you concept of clock signal and delay. Clock is a control signal that allows the changes in the states of digital circuits to occur only at well–defined time intervals, as if they were controlled by a clock. It should be noted that either rising clock edges, , or falling edges, , is lead to changes in the states not its logic level (0 or 1). Actually clock is a periodic signal that is equal to 1 at regular time intervals to suggest that this is how the clock signal usually appears in a real system. Connecting an odd number of inverter gates in series, you will make a clock signal. Fig 1.5 depicts the simple clock pulse circuit. You should connect the last gate output to first gate input. Then look at the output signal on oscilloscope and measure its frequency. Then calculate average delay of each gate and demonstrate your result to your TA. Keep in mind, more number of inverter gates, more accurate results. 9ELEN 248 Laboratory Manual, Lab 1 Clock signal Odd number of inverter gates Fig. 1.5: Construction of a clock signal using inverter gates 1.5 Post lab None. 10ELEN 248 Laboratory Manual, Lab 2 Lab 2: Introduction to Max+Plus II 2.1 Introduction In this lab you will repeat the experiments from Lab 1; however, this time you will be using the Altera MAX+plus II software to program the Altera EPM7128S P(rogrammable) L(ogic) D(evice). This is the simulation technique we will use for the rest of the semester. 2.2 Background The only background material you need is an understanding of combinational circuits, covered in Lab 1. 2.3 Prelab None. 2.4 Lab Procedure To begin this lab, log on to the computer using your Novell Network login. A unique username and password is automatically assigned to every student that is registered for an electrical engineering laboratory. The username has the format “fml6789” where “fml” represent your initials and “6789” represents the last 4 digits of your student ID number. Your password is your entire student ID number, including dashes. Your account may not be active during the first couple of weeks of lab, so you may have to obtain a temporary login from your TA. After you have logged in, find the Max+plus Icon and run the program (double-click the icon). Once in Max+, create a new file by clicking on the toolbar icon at the far left. A dialog window will appear and will ask what type of file you wish to create. Choose the .gdf file. This should be the default choice. Now proceed to the first experiment. 2.4.1 Experiment 1 As in Lab 1, we will look at the behavior of some basic logic gates. We will first program an inverter (not) gate. To do this, left click on your .gdf file at the location where you would like the inverter to be placed. You can always move it later. Then go to the Symbol pull down menu and select Enter Symbol. A dialog window will appear (see Figure 2.1). Type “not” on the top line of the dialog window and hit enter. An inverter gate will appear in your .gdf file. We now need to create an input pin and an output to connect to the inverter gate. Repeat the procedure above, but type “input” in the dialog window. This will give you an input pin. Now create an “output” pin. To create the wires to connect the pins to the gate, click on the line tool button, which is the 11ELEN 248 Laboratory Manual, Lab 2 Fig. 2.1: Enter Symbol dialog box button on the left with a picture of a right angle. You can then drag a straight line with one 90- degree bend to connect any two gates or wires in the schematic. There are two important things to remember when creating schematics in Max+II. First, always look for a dot to appear whenever you connect two wires together. If there is no dot, you cannot be sure that there is (isn’t) a connection. Second, make sure that your wires are not laid across the dotted-line borders of your symbols, as this can cause errors. Next, you must name your input and output pins. You can do this by double-clicking on the name shown (which defaults to PIN NAME) and typing a new name. Not that all pin names must be unique. Before you can compile your simulation file and program the PLD, you must make your .gdf file the “current project”. The command to set the project name to your current file is found in the File menu. Scroll down to Project, which opens a submenu. Inside this submenu, scroll down to Set Project to Current File. Note that if you have not yet saved your program, you must do so at this point. All files must be saved to your Zip disk, which is the E: drive. Now you can compile your circuit. This command can be found in the File menu, under Project, as before. In the same submenu, click Save and Compile. The compiler will open a window containing messages about your program’s status. At this point, one of two things will happen. Either you will see messages in red, indicating errors, or the program will compile successfully. 12ELEN 248 Laboratory Manual, Lab 2 Note that you may see warnings, but these can generally be ignored. If your file has errors then you will need to go back and correct them. Under some circumstances, you may double (left) click on the red message and the program will return to the .gdf file and highlight, in red, the part of the circuit that the program believes is in error. Before you can program the EPM7128S PLD that is embedded in the Altera circuit board, you must assign specific PLD pin numbers to the input and output pins you have placed in your .gdf file. Many of the pins on the PLD have been prewired to switches, LEDs, or pushbuttons. Page 16 provides you with a pin-out that will describe these connections. To assign a pin number to one of your input/output pins, first right click on the pin. Choose Assign, then Pin/Location/Chip from the resulting pull down menu. A new dialog box will appear. The first time you specify a pin number, you have to push the Assign Device button and choose the PLD part number EPM7128S. Click OK to return to the first dialog box. Now place a pin number in the Pin box and click OK. Repeat this procedure for each pin in your .gdf file. Remember, you only have to Assign Device once. You will find the Programmer in the MAX+plus II pull down menu; click on Program, and your program will be written to the chip. After programming is complete, observe the behavior of the inverter circuit. Suppose A is the input to the inverter and Y is the observed response (H or L). Fill in Table 2.1. Remember that if an LED is on, it is indicating a logic L. Tab. 2.1: Inverter logic behavior 2.4.2 Experiment 2 Perform the above experiment with gates and2, or2, nand2, nor2, and xor. Since each of these gates has two inputs and one output, you will need to create another input pin. Fill in Table 2.2. Tab. 2.2: Basic logic gate logic behavior 13ELEN 248 Laboratory Manual, Lab 2 2.4.3 Experiment 3 Create the circuit in Fig. 2.2 using the Max+II software and complete the logic behavior Table 2.3. Assume positive logic. Demonstrate this circuit to your TA. Fig. 2.2: Circuit A Tab. 2.3: Circuit A logic behavior 2.4.4 Experiment 4 This experiment will introduce you one out of huge number of blocks that Max+II provide you to use in constructing digital circuits. Each of these blocks has its own special function. Accessing to each block, repeat the procedure in experiment 1 and type the name of the block in the dialog window. In this experiment you will connect three inputs and one output to the 21mux block and then fill in its truth table shown in Fig. 2.3. Guess its function and demonstrate to your TA. 14ELEN 248 Laboratory Manual, Lab 2 A B F C 21mux Fig. 2.3: 21mux block Tab. 2.4: Multiplexer 2:1 logic behavior 2.5 Postlab There is no postlab requirement for Lab 2. The prelab for Lab 3 is due at the beginning of lab next week. 15

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