# VLSI design lab manual

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LABORATORY MANUAL VLSI DESIGN LAB EE-330-F th (VI Semester) Prepared By: Vikrant Verma B. Tech. (ECE), M. Tech. (ECE) Department of Electrical & Electronics Engineering BRCM College of Engineering & Technology Bahal-127028 (Bhiwani) Modified on 14 November 2014 VLSI Design Lab Manual Page 1 EXPERIMENT – 1 Aim: Write the VHDL Code & Simulate it for the following gates. Two I/P AND Gates. Two I/P OR Gates. Two I/P NAND Gates Two I/P NOR Gates. Two I/P Ex-OR Gates. NOT Gates. Apparatus used: XILINX 8.1 Software installed in a PC. Theory: VLSI Design Lab Manual Page 4 Program: i) Behavior Model if two I/P AND Gates. Library IEEE; Use IEEE.std_logic_1164_all; Use IEEE.std_logic_arith_all; Entity and_2 is Port (a, b: in bit; z: out bit); End and_2; Architecture and_2_beh of and_2 is Begin process (a, b) Begin If (a=’0’ and b=’0’) then Z=’0’; ElsIf (a=’0’ and b=’1’) then Z=’0’; ElsIf (a=’1’ and b=’0’) then Z=’0’; ElsIf (a=’1’ and b=’1’) then Z=’1’; End if; End process; End and_2_beh; ii) Behavior Model if two I/P OR Gates Library IEEE; Use IEEE.std_logic_1164_all; Use IEEE.std_logic_arith_all; Entity OR_2 is Port (a, b: in bit; z: out bit); End OR_2; VLSI Design Lab Manual Page 5 Architecture OR_2_beh of OR_2 is Begin process (a,b) Begin If (a=’0’ and b=’0’) then Z=’0’; Elsif (a=’0’ and b=’1’) then Z=’1’; Elsif (a=’1’ and b=’0’) then Z=’1’; Elsif (a=’1’ and b=’1’) then Z=’1’; End if; End process; End OR_2_beh; iii) Behavior Model if two I/P NAND Gates Library IEEE; Use IEEE.std_logic_1164_all; Use IEEE.std_logic_arith_all; Entity NAND_2 is Port (a, b: in bit; z: out bit); End NAND_2; Architecture NAND_2_beh of NAND_2 is Begin process (a, b) Begin If (a=’0’ and b=’0’) then Z=’1’; Elsif (a=’0’ and b=’1’) then Z=’1’; Elsif (a=’1’ and b=’0’) then Z=’1’; Elsif (a=’1’ and b=’1’) then VLSI Design Lab Manual Page 6 Z=’0’; End if; End process; End NAND_2_beh; iv) Behavior Model if two I/P NOR Gates Library IEEE; Use IEEE.std_logic_1164_all; Use IEEE.std_logic_arith_all; Entity NOR_2 is Port (a, b: in bit; z: out bit); End NOR_2; Architecture NOR_2_beh of NOR_2 is Begin process (a, b) Begin If (a=’0’ and b=’0’) then Z=’1’; Elsif (a=’0’ and b=’1’) then Z=’0’; Elsif (a=’1’ and b=’0’) then Z=’0’; Elsif (a=’1’ and b=’1’) then Z=’0’; End if; End process; End NOR_2_beh; v) Behavior Model if two I/P EX-OR Gates Library IEEE; Use IEEE.std_logic_1164_all; Use IEEE.std_logic_arith_all; VLSI Design Lab Manual Page 7 Entity EXOR_2 is Port (a, b: in bit; z: out bit); End EX-OR_2; Architecture EXOR_2_beh of EXOR_2 is Begin Process (a, b) Begin If (a=’0’ and b=’0’) then Z=’0’; Elsif (a=’0’ and b=’1’) then Z=’1’; Elsif (a=’1’ and b=’0’) then Z=’1’; Elsif (a=’1’ and b=’1’) then Z=’0’; End if; End process; End EXOR_2_beh; vi) Behavior Model if two I/P NOT Gates Library IEEE; Use IEEE.std_logic_1164_all; Use IEEE.std_logic_arith_all; Entity NOT_2 is Port (a: in bit; z: out bit); End NOT_2; Architecture EXOR_2_beh of EXOR_2 is Begin Process (a) Begin If (a=’0’) then Z=’1’; VLSI Design Lab Manual Page 8 Elsif (a=’1’) then Z=’0’; End if; End process; End NOT_2_beh; Precautions: Make sure that there is no syntax and semantic error. Result: All the VHDL codes of AND, OR, NAND, NOR, EX-OR and NOT gates are simulated & found correct. Typical viva-voce questions for reference: Q1: The output will be a LOW for any case when one or more inputs are zero in a(n): A. OR gate B. NOT gate C. AND gate D. NAND gate Ans: AND gate Q.2: If a signal passing through a gate is inhibited by sending a low into one of the inputs, and the output is HIGH, the gate is a(n): A. OR gate B. NOT gate C. AND gate D. NAND gate Ans: NAND gate Q.3: A single transistor can be used to build which of the following digital logic gates? A. OR gate B. NOT gate C. AND gate D. NAND gate Ans: NOT gate VLSI Design Lab Manual Page 9 EXPERIMENT – 2 Aim: Write behavior model of 1- bit Comparator. Apparatus used: XILINX 8.1 Software installed in a PC. Theory: Program: Library IEEE; Use IEEE.std_logic_1164_all; Use IEEE.std_logic_arith_all; Entity CMP_2 is Port (a, b: in bit; ALB, AGB, AEB: out bit); End CMP_2; Architecture CMP_2_beh of CMP_2 is Begin Process (a, b) VLSI Design Lab Manual Page 10 Begin If (a=’0’ and b=’0’) then ALB=’0’; AGB=’0’; AFB=’1’; Elsif (a=’0’ and b=’1’) then ALB=’1’; AGB=’0’; AFB=’0’; Elsif (a=’1’ and b=’0’) then ALB=’0’; AGB=’1’; AFB=’0’; Elsif (a=’1’ and b=’1’) then ALB=’0’; AGB=’0’; AFB=’1’; End if; End process; End CMP_2_beh; Precautions: Make sure that there is no syntax and semantic error. Result: All the VHDL codes of 1- bit Comparator is simulated & synthesized. Typical viva-voce questions for reference: Q.1: How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? Ans: Four. Q.2: What is an Identity Comparator ? Ans: An Identity Comparator is a digital comparator that has only one output terminal for when A = B either “HIGH” A = B = 1 or “LOW” A = B = 0 Q.3: What is Magnitude Comparator? Ans: A Magnitude Comparator is a type of digital comparator that has three output VLSI Design Lab Manual Page 11 terminals, one each for equality, A = B greater than, A B and less than A B. Q.4: What is the purpose of a Digital Comparator? Ans: The purpose of a Digital Comparator is to compare a set of variables or unknown numbers, for example A (A1, A2, A3, …. An, etc) against that of a constant or unknown value such as B (B1, B2, B3, …. Bn, etc) and produce an output condition or flag depending upon the result of the comparison. For example, a magnitude comparator of two 1-bits, (A and B) inputs would produce the following three output conditions when compared to each other. VLSI Design Lab Manual Page 12 EXPERIMENT – 3 Aim: Write a program for behavior model of 4- bit Comparator. Apparatus used: XILINX 8.1 Software installed in a PC. Theory: Program: Library IEEE; Use IEEE.std_logic_1164_all; Use IEEE.std_logic_arith_all; Entity COM_2 is Port (a, b: in bit_vector (3 down to 0); z: out bit_vector (2 down to 0)); End COM_2; Architecture COM_2_beh of COM_2 is Begin Process (a, b) Begin If (a=b) then Z=’100’; Elsif (ab) then Z=’010’; Elsif (ab) then Z=’001’; End if; End process; VLSI Design Lab Manual Page 13 End COM_2_beh; Precautions: Make sure that there is no syntax and semantic error. Result: The VHDL code of 4- bit Comparator is simulated & synthesized. Typical viva-voce questions for reference: Q.1: What is comparator? Ans: A digital comparator or magnitude comparator is a hardware electronic device that takes two numbers as input in binary form and determines whether one number is greater than, less than or equal to the other number. Q.2: What are uses of comparator? Ans: Comparators are used in central processing unit s (CPUs) and microcontrollers (MCUs). Examples of digital comparator include the CMOS 4063 and 4585 and the TTL 7485 and 74682-'89. Q.3: What is the voltage comparator? Ans: The analog equivalent of digital comparator is the voltage comparator. Many microcontrollers have analog comparators on some of their inputs that can be read or trigger an interrupt. Q.4: What is the no. of outputs in 4- bit comparator? Ans: Three output. VLSI Design Lab Manual Page 14 EXPERIMENT – 4 Aim: Write the VHDL code & simulate it for 4:1 Multiplexer & 4:1 Demultiplexer. Apparatus used: XILINX 8.1 Software installed in a PC. Theory: VLSI Design Lab Manual Page 15 Program: 4-to-1 Multiplexer’s Behavior Model: Library IEEE; Use IEEE.std_logic_1164_all; Use IEEE.std_logic_arith_all; Entity MUX_2 is Port (i0, i1, i2, i3, s0, s1: in bit; z: out bit); End MUX_2; Architecture MUX_2_beh of MUX_2 is Begin Process (so, s1) Begin If (s1=’0’ and s0=’0’) then Z=’i0’; Elsif (s1=’0’ and s0=’1’) then Z=’i1’; Elsif (s1=’1’ and s0=’0’) then Z=’i2’; Elsif (s1=’1’ and s0=’1’) then Z=’i3’; End if; End process; End MUX_2_beh; 1-to-4 Demultiplexer: VLSI Design Lab Manual Page 16 1-to-4 Demultiplexer’s Behavior Model: Library IEEE; Use IEEE.std_logic_1164_all; Use IEEE.std_logic_arith_all; Entity DEMUX_2 is Port (a, s0, s1: in bit; z: out bit_vector (3 down to 0)); End DEMUX_2; Architecture DEMUX_2_beh of DEMUX_2 is Begin Process (so, s1) Begin If (s1=’0’ and s0=’0’) then Z (0) =a; Z (1) =’0’; Z (2) =’0’; Z (3) =’0’; Elsif (s1=’0’ and s0=’1’) then Z (0) =’0’; VLSI Design Lab Manual Page 17 Z (1) =a; Z (2) =’0’; Z (3) =’0’; Elsif (s1=’1’ and s0=’0’) then Z (0) =’0’; Z (1) =’0’; Z (2) =a; Z (3) =’0’; Elsif (s1=’1’ and s0=’1’) then Z (0) =’0’; Z (1) =’0’; Z (2) =’0’; Z (3) =a; End if; End process; End DEMUX_2_beh; Precautions: Make sure that there is no syntax and semantic error. Result: a) All the VHDL codes of 4-to-1 Multiplexer is simulated & synthesized. b) All the VHDL codes of 1-to-4 Demultiplexer is simulated & synthesized. Typical viva-voce questions for reference: Q.1 A basic multiplexer principle can be demonstrated through the use of a? Ans. Rotary Switch. Q.2 What is the function of an enable input on a multiplexer chip? Ans. To active the entire chip. Q.3 Will multiplexing create additional harmonics in the system? Ans. No, the total harmonic content while using multiplex mode is no worse than using normal SCR dimmer firing modes. Q.4 Can you accidentally switch a dimmer to multiplex mode? Ans. To minimize the chances of this occurring, a number of steps are required to configure a VLSI Design Lab Manual Page 18 dimmer for multiplexing at the sensor dimmer rack. Each action requires operator confirmation and dimmer status is clearly displayed at all times during setup. VLSI Design Lab Manual Page 19 EXPERIMENT – 5 Aim: Write a program for behavior model of BCD-to-Seven Segment Decoder. Apparatus used: XILINX 8.1 Software installed in a PC. Theory: BCD Input’s Output’s A B C D a b c d e f g 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 VLSI Design Lab Manual Page 20 Program: Library IEEE; Use IEEE.std_logic_1164_all; Use IEEE.std_logic_arith_all; Entity BCD_2 is Port (b: in bit_Vector (3 down to 0); z: out bit_vector (6 down to 0)); End BCD_2; Architecture BCD_2_beh of BCD_2 is Begin Process (b) Begin Case B is When “0000”= S=”1111110”; When “0001”= S=”0110000”; When “0010’= S =”1101101”; When “0011”= S=”1111001”; When “0110”= S=”1011111”; When”0111”= S=”1110000”; When”1000”= S=”1111111”; When”1001”= S=”1110011”; When other = S=”000000”; End case; End process; VLSI Design Lab Manual Page 21 End BCD_Beh; Precautions: Make sure that there is no syntax and semantic error. Result: All the VHDL codes of BCD-to-Seven Segment is simulated & synthesized. Typical viva-voce questions for reference: Q.1 What is the full the full form of BCD? Ans: Binary Coded Decimal. Q.2 What is the function of decoder? Ans: In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output n codes are different. E.g. n-to-2 , binary-coded decimal decoders. Q.3 What is the full form of LCD? Ans: Liquid Crystal Display. Q.4 What is 7-Segment? Ans: A standard 7-segment LED display generally has 8 input connections, one for each LED segment and one that acts as a common terminal or connection for all the internal display segments. Some single displays have also have an additional input pin to display a decimal point in their lower right or left hand corner. VLSI Design Lab Manual Page 22

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