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VLSI Design Computer Laboratory Computer Science Tripos Part 2 Peter Robinson Michaelmas 2000 New Museums Site Pembroke Street Cambridge CB2 3QG http://www.cl.cam.ac.uk/ © Peter Robinson, 1984-2000. All rights reserved.VLSI Design Introduction This course will introduce the design of very large scale integrated circuits. The material develops an understanding of the whole spectrum from semiconductor physics through transistor-level design and system design to architecture, and promotes the associated tools for computer aided design. Syllabus The course consists of 12 lectures divided into three main headings: Transistor design • Semiconductor technology. Semiconductors, junction, diode, transistor. Bipolar devices. Structure and operation of MOS transistor. Simple logic. MOS layers, stick diagrams. Layout of an invertor. Transmission gates • and pass transistor logic. • Combinatorial logic. NOR and NAND in nMOS and CMOS. Compound gates. Delays. • Logic design. Stereotyped design and PLAs. System design • Clocking and registers. Storage elements and sequential machines. Dynamic logic. • Memory design. • System design. Gates, shifters, adders, counters, memory, PLAs. • Fabrication. Design rules and lambda rules. Performance and large loads. Scaling. Computer-aided design • Semi-custom techniques. Gate arrays, standard cell, full custom. • CAD systems and algorithms. Design flow. Circuit descriptions. • Simulation and testing. • Self-timed circuits. Objectives On completing the course, students should be able to: • Describe the structure and operation of an MOS transistor. • Design simple logic in CMOS. • Compare different designs as circuits, stick diagrams and layout. • Explain gate matrix and PLA design in CMOS. • Apply clocked design for dynamic logic and storage. • Discuss different approaches to the design of memory. • Describe the modules making up a processor. Explain the fabrication process and analyse its implications. • Michaelmas 2000 1VLSI Design • Compare different approaches to the implementation of systems. • Describe the rôle of computer aided design. • Explain algorithms for simulation, placement and routing. • Discuss the relevance and design of self-timed circuits. It should be pointed out that these notes do not constitute a complete transcript of all the lectures and they are not a substitute for text books. They are intended to give a reasonable synopsis of the subjects discussed, but they give neither complete descriptions nor all the background material. Acknowledgements The presentation of the first half of this material is based on a course taught by Randy Katz, of the University of California at Berkeley, and Gaetano Borriello, now of the University of Washington. Simon Moore prepared the section on self-timed circuits. Enormous thanks are due to Jenni Cartwright for transcribing the notes. Appropriate books The following books are relevant for the course: • S Augarten: State of the art, Ticknor & Fields 1983. A pictorial history of semiconductors, just right for your coffee table. • GM Blair: MOS circuit design, Chartwell-Bratt 1992. SH Gerez: Algorithms for VLSI design automation, Wiley 1999. • • J Mavor, MA Jack & P Denyer: Introduction to MOS LSI design, Addison-Wesley 1983. A gentle introduction, beginning to show its age. • CMead& LConway: Introduction to VLSI systems, Addison-Wesley 1980. The old classic, emphasis on nMOS. • NHE Weste & K Eshragian: Principles of CMOS VLSI design (2nd edition), Addison- Wesley 1993. The new classic? • WWolf: Modern VLSI design - a system approach, Prentice-Hall 1994. Colouring conventions You will need a set of colouring pencils (including yellow, green, brown, red and blue) to gloss the diagrams in these notes during the lectures. The following conventions are used for the colours here: Yellow Green Brown Red Blue Black A copy of these notes (and other relevant teaching material) can be read on-line by following the links from http://www.cl.cam.ac.uk/Teaching/. This may be particularly helpful when checking colours. Access is limited to computers within the Computer Laboratory. Michaelmas 2000 2VLSI Design Semiconductor technology Semiconductors can be made from crystalline silicon into which impurities have been introduced: A high valency implant such as phosphorous gives free electrons, creating an n-type region. A low valency implant such as boron gives free holes, creating a p-type region. The junction of an n-type and a p-type region in a single crystalline lattice creates a diode which only conducts if it is forward biased with the p-type region (the anode) more positive than the n-type region (the cathode). +- p n A light emitting diode has the additional property that it glows when current is flowing through it. It is prudent to limit this current to a few milli-Amps by means of a kilohm series resistor, or it glows very brightly, but only for a short time. Digital switching Most digital logic is based on the idea of switching signals between a high voltage (which we will usually treat as being 5V, although modern systems more commonly use 3.3V or less) and a low voltage (0V, or ground). The sense may be determined by current flowing or not (as in bipolar circuits) or by the presence or absence of charge (as in MOS circuits). A logic function takes some input signals and computes an output function using pull-up and pull-down circuits which may be passive (always switched on) or active (selectively switched). Q A B Passive pull-up and active pull-down The diagram shows a circuit with an active pull-down and a passive pull-up. The pull-down can be thought of as a remote-control switch, usually made from transistors but possibly relays or valves. A further complexity with MOS circuits is that the charge on wires persists after they have ceased to be driven; this means that the wires have a memory (typically lasting a thousandth of a second or so) of the last value driven on them. Michaelmas 2000 3VLSI Design Bipolar circuits A bipolar transistor is formed by a sandwich of n-type, p-type and n-type regions in a single crystalline lattice. It can be thought of two diodes connected anode-to-anode such that a current through the forward biased diode overwhelms the reverse biased diode. collector collector n+ base base p n emitter emitter npn bipolar transistor A small current flowing from the base to the emitter of an npn transistor induces a large current from the collector to the emitter. A pnp transistor has the opposite polarity. These can be used to construct a NAND gate using transistor-transistor logic (TTL). Q A B TTL NAND gate The two transistors on the left calculate the logical function and that on the right is simply an invertor. Sometimes this is followed by an additional buffer for a totem pole output. With a 1k7 Ohm pull-up, about 1 mA flows through the gate whenever an input is high and the gate then dissipates 5 mW. There are also difficulties in finding the right sizes for the transistors and resistor. MOS circuits An enhancement mode, n-channel, metal-oxide-silicon field-effect transistor (nMOS FET) is formed on a crystal of p-type silicon. Two n-type regions (known as diffusion) lie on either side of a region of the p-type substrate which is covered by a thick layer of insulating silicon dioxide (or oxide) and a metal plate. Michaelmas 2000 4VLSI Design drain drain n p gate base n source source n-channel enhancement mode metal-oxide-semiconductor field-effect transistor When the gate is positive with respect to the source, an n-type channel is formed under the gate and current is conducted from drain to source. Even when turned on, a MOS transistor has a resistance of about 10 kΩ . The construction of the transistor is symmetric with respect to the source and drain - the labels merely indicate the relative voltages. This contrasts with the different processing used to make the collector and emitter of a bipolar transistor. A p-channel MOS FET has the opposite polarity and conducts when its gate is low. However, the resistance of a p-type channel is about 2½ times that of an n-type channel of the same size. In integrated circuits, the metal gate is replaced by one made from polycrystalline silicon (or polysilicon) for ease of fabrication. The nMOS transistor operate in three modes: off when V V gs t saturated when V V and V V –V gs t ds gs t linear when V V and V V –V gs t ds gs t where Vt is the threshold voltage ( = 0.2 V = 1Vfor a 5Vsystem) dd Note that, even when the transistor is turned on, the source voltage can not rise above the gate voltage less the threshold voltage. The threshold voltage can be adjusted by implanting further impurities into the channel regions. It canevenbe made negative(V =-0.8V = -4V), giving a depletion mode nMOS FET which t dd always conducts. This can be used as a compact way of making a resistor. nMOS An nMOS NOR gate can be made with two n-type pull-down transistors in parallel and a passive pull-up. There are three ways that the pull-up could be made: A resistor – using polysilicon (which is the most resistive material available in a MOS process) this would have to be several hundred times the size of the pull-down transistor. An enhancement mode transistor with its gate wired high – this could never pull the output above V –V . dd t Michaelmas 2000 5VLSI Design A depletion mode transistor with its gate wired to its source is used in practice. Q A B NOR gate in nMOS Current flows mainly when the gate is switched and the output is charged or discharged; only a small leakage current flows otherwise. With a 40 kΩ pull-up and a 10 kΩ pull-down in series, a current of 0.1 mA flows when an input is high and 0.5 mW is dissipated. When the pull-down network is switched on, the depletion mode pull-up and the enhancement mode pull-down form a potential divider, and the output voltage approaches the appropriate ratio of the supply voltage – usually the ratio is 1:4, so the output falls to 1 V. CMOS A CMOS NOR gate can be made with two n-type pull-down transistors in parallel and two p- type transistors in series as an active pull-up. The complementary Boolean circuits in the pull- up and pull-down networks give the technology its name. A B Q NOR gate in CMOS Current only flows when the gate is switched and the output signal (which may be regarded as a capacitor) is charged or discharged, making the power consumption very low. A further advantage of CMOS over nMOS and bipolar circuitry is that is does not rely on the ratio of the resistances in the pull-up and pull-down networks to determine the output voltage. The output switches between 0 V and 5 V rather than between about 1 V and 5 V. The disadvantage is the additional complexity of the complementary circuit. Michaelmas 2000 6VLSI Design Simple logic in MOS There are several layers in an nMOS chip: a p-type substrate paths of n-type diffusion a thin layer of silicon dioxide paths of polycrystalline silicon a thick layer of silicon dioxide paths of metal (usually aluminium) a further thick layer of silicon dioxide with contact cuts through the silicon dioxide where connections are required. The three layers carrying paths can be considered as independent conductors that only interact where polysilicon crosses diffusion to form a transistor. These tracks can be drawn as stick diagrams with diffusion in green polysiliconinred metal in blue using black to indicate contacts between layers and yellow to mark regions of implant in the channels of depletion mode transistors. WithCMOS therearetwotypes of diffusion:n-type is drawningreenandp-typeinbrown. These are on the same layers in the chip and must not meet. In fact, the method of fabrication required that they be kept relatively far apart. Modern CMOS processes usually support more than one layer of metal. Two are common and three or more are often available. Actually, these conventions for colours are not universal; in particular, industrial (rather than academic) systems tend to use red for diffusion and green for polysilicon. Moreover, a shortage of coloured pens normally means that both types of diffusion in CMOS are coloured green and the polarity indicated by drawing a circle round p-type transistors or simply inferred from the context. Colouring for multiple layers of metal are even less standard. There are three ways that an nMOS invertor might be drawn: Michaelmas 2000 7VLSI Design Q A Invertor designs in nMOS The three different representations are useful in different contexts: a circuit diagram – used to plan the logic of the system; a stick diagram – used to plan the topology of a layout, committing signals to particular layers; and layout – final decisions of sizes The equivalent pictures in CMOS are: A Q Invertor designs in CMOS This layout shows the input arriving through polysilicon on the left and the output leaving through metal on the right. A second layer of metal might be used to allow connections above and below the invertor with a third layer left free to run other, quite separate, signals (such as a global clock) across the top of the invertor. The following design runs power and ground in the second metal layer and signals in the first, with the polysilicon hidden underneath it. Michaelmas 2000 8VLSI Design Transmission gates It is possible to compute logic functions without making logic gates – networks of MOS transistors can be connected together directly. These are known as transmission gates.(Of course, the transistors still have gates, but that is a different use of the word, as also would be logic gates). With CMOS, the nMOS transistors are good at conducting low signals and the pMOS transistors are good at conducting high signals, so transmission gates are often made from a pair of complementary transistors. When the control signal S is high, the transmission gate conducts logic signals of either sense in either direction. A special symbol is used for the CMOS transmission gate: S S S’ S’ Pass transistor logic MOS transistors can be used simply as switches to steer current using pass transistor logic. Consider a simple multiplexor with 2 control inputs, S &S , 4 data inputs, I , and a single 0 1 n output, Z. The function can be specified by a simple table: Michaelmas 2000 9VLSI Design S S Z 1 0 00 A 0 01 A 1 10 A 2 11 A 3 This can be implemented using nMOS pass transistors as follows: S1 S0 A0 Q A1 A2 A3 S1 S0 S1 S0 A0 Q A0 Q A1 A1 A2 A2 A3 A3 Multiplexor using pass transistors Note how a mixed notation (inverters and transistors or even invertors in a stick diagram) can be used. The second stick diagram uses depletion mode transistors as conductors to avoid going into metal, giving a more compact layout. This could be implemented in CMOS even more simply, although care needs to be taken about mixing the two types of diffusion (or else a diode would be formed): Michaelmas 2000 10VLSI Design S1 S0 S1 S0 A0 Q A0 Q A1 A1 A2 A2 A3 A3 The design would also work better if transmission gates were used. As a further example, consider a tally circuit to count the number of 1s in an input word, giving the answer in unary. The specification is: X X X Z Z Z Z 2 1 0 0 1 2 3 00010 00 00101 00 01001 00 01100 10 10001 00 10100 10 11000 10 11100 01 This can be implemented using nMOS pass transistors as follows: Michaelmas 2000 11VLSI Design Z 3 Z2 Z1 Z0 X2 X1 X0 Note how each output signal in pass transistor logic is driven precisely once for any pattern of input signals – no signal should be left undriven and there should be no contention for any output value. The idea of repeating a simple structure to make a complicated circuit is important in VLSI design. A caution The source potential of a MOS transistor can not rise above the gate potential less the threshold voltage. When using a chain of pass transistors, this results in a significant voltage drop across the first transistor, and rather less across subsequent ones. The attenuated signal must be restored by giving the gate that it drives a more sensitive (larger) pull-down transistor. A signal that has been switched by a pass transistor must not itself control a further pass transistor, or a second voltage drop would occur: 5 44 3 Michaelmas 2000 12VLSI Design Combinatorial logic In nMOS, the NOR gate has better speed and area characteristics than the NAND gate: It is also possible to compute complex functions such as X ⋅Y + Z in one step: In CMOS, the NAND gate has better speed and area characteristics than the NOR gate: Again, complex logic is possible: Michaelmas 2000 13VLSI Design The complementary pull-up network becomes tedious and may be replaced by a p-type transistor tied low, rather like an nMOS depletion load (but this wastes power). Alternatively, dynamic (or clocked) logic may be used – see below. Delays The delay through a MOS gate is simply the time that it takes to charge (or discharge) its output signal above (or below) the threshold voltage of any transistors in further circuitry that it drives. The voltage on the output will move asymptotically towards its final voltage in an exponential decay whose time constant, RC, is dominated by the product of the resistance of the channel in the transistor driving the output and the capacitance of the output signal. The series resistance can be reduced (speeding up the gate) by increasing the size of the driving transistor, allowing a trade to be made between speed and size. The capacitance is determined by the length of the output track and, significantly, by the area of the gates that it drives; this in turn depends on the fan-out and the power of the gates in the fan-out. For an nMOS invertor, the ratio of the resistances of the pull-up and pull-down transistors determines the sensitivity of the invertor and also the shape of the curve describing the output voltage after a change of the input. V t Note that an input change from 0V to 5V results in an output swing from 5V to 1V and also that there are differential delays for falling and rising outputs. A simple CMOS invertor will also have different resistances of p-type and n-type channels. However, this can be resolved by changing the sizes of the transistors, giving a symmetric response as well as full logic swing. Michaelmas 2000 14VLSI Design Logic design Consider the design of a circuit to compare two signals and test them for equality – an exclusive NOR gate. This has the following definition: AB A=B 00 1 01 0 10 0 11 1 This can be implemented in a number of ways. Firstly using NOR or NAND gates: A A Q Q B B This leads to an nMOS implementation using 12 transistors or CMOS using 16 (or 18 with the extra invertor). However, a more compact solution can be achieved using pass transistors: B B AQ A Q The nMOS version uses 6 transistors and the CMOS version uses 8 (or only 4 if the complementary parts of the transmission gates shown in grey are omitted). A little further thought reduces this to only 3 transistors: Michaelmas 2000 15VLSI Design AQ AQ B B However, these simpler circuits must be used with care. The inputs to the pass transistor logic must be driven signals, not just potentials, or else there might be charge sharing (reverse flow of information). The 3-transistor circuits have passive pull-ups and so will dissipate power. Stereotyped design Random logic consisting of nMOS NOR gates can be laid out in a regular form as a Weinberger gate array. For example, the 12 transistor exclusive NOR gate could be laid out as follows: A B Q RandomCMOS canbelaidout similarlyasa gatematrix: A Q B This exampleuses onlyNAND gates andaninvertor, but clearlyarbitrarygates including transmission gates could be laid out in this way. Both of these schemes have the advantage that they are amenable to automatic layout in a reasonable space. Michaelmas 2000 16VLSI Design PLAs When several different functions of a set of input signals are required, a programmable logic array (PLA) may be useful. Any boolean function can be reduced to disjunctive normal form - a sum (OR) of products (AND) of the inputs and their inverses. The product terms are referred to as minterms. Using only n-type transistors, it is convenient to remember de Morgan’s law when computing X ⋅Y = X + Y the minterms: The exclusive NOR function can be thus written as: Q = A ⋅ B + A⋅ B = A + B + A + B This leads to the following nMOS layout: A B Q Note how distributed gates are used in the pull-down circuitry of the minterms. The regular structure of the PLA again makes it amenable to automatic layout. This is particularly useful when several different functions are being computed that share minterms. Michaelmas 2000 17VLSI Design Clocked logic Data can be moved through sections of combinational logic under the control of a clock signal. It is convenient to use a two-phase non-overlapping clock: Ø 1 Ø 2 Ø and Ø can be generated on the chip from a single external clock: 1 2 ∅ ∅ ∅ ∅ ∅ ∅ ∅ ∅ 1 ∅ ∅ ∅ ∅ 2 The durations and separations of the high periods can be controlled by introducing delay into the feedback loops. Shift register A shift register can be made by connecting a sequence of inverters together using pass transistors switched on alternate clock phases: ∅ ∅ ∅ ∅ ∅ ∅ ∅ ∅ ∅ ∅ ∅ ∅ 1 2 1 This canbe extendedinparalleltoshift words rather thanbits: ∅ ∅ ∅ ∅ ∅ ∅ ∅ ∅ ∅ ∅ ∅ ∅ 1 2 1 The clock signal can be combined with a control signal to give different modes of operation. For example, the shift register could rotate the bits in a word: Michaelmas 2000 18

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