Design of Power Sequential Circuit by Adiabatic Techniques

clock gated low power sequential circuit design and power reduction for sequential circuit using merge flip-flop technique and design sequential circuit state diagram
Dr.JohnGates Profile Pic
Published Date:09-11-2017
Your Website URL(Optional)
I.J. Intelligent Systems and Applications, 2015, 08, 45-50 Published Online July 2015 in MECS ( DOI: 10.5815/ijisa.2015.08.06 Design of Low Power Sequential Circuit by using Adiabatic Techniques Priyanka Ojha ITM University/Department of EECE, Gurgaon, 122001, India Email: Charu Rana ITM University/Department of EECE, Gurgaon, 122001, India Email: Abstract— Various adiabatic logic circuits can be used for minimizing the power dissipation. To enhance the functionality and performance of circuit two adiabatic logic families PFAL and ECRL have been used and compared with CMOS logic circuit design. In this paper, A MASTER-SLAVE D flip-flop is proposed by the use of SPICE simulation on 90nm technology files. The simulation result shows that PFAL is a better energy saving techniques then ECRL logic circuit. Index Terms— Adiabatic Switching, Energy Dissipation, AC Power Supply, Inverter, D Latch and D Flip-Flop. I. INTRODUCTION The expression „Adiabatic‟ is taken from a Greek language which means no energy transfer with outer environment, this process is known as a thermodynamic. Fig. 1. Basic CMOS circuit design So the dissipated heat loss in adiabatic logic families is very less. But in CMOS logic design, charge flow in the In a charging process of output, a size of charge circuit is studied and many methods can be used for delivered to the load is 1. minimizing power dissipation in basic CMOS design like: reducing the power supply and switching activities. A (1) combination of above all is important in portable systems Where, is load capacitance and is the power which have some common issues such as weight, size and supply. If the voltage is 0 then no energy is conveyed by life of battery 2, 4, 27. current returning through ground terminal. A node In today‟s modern era power dissipation is a primary charged up with energy is 1. concern in many application especially based on high performance battery operated and portable systems. By (2) reducing the heat dissipation many digital signal- The half of power is stored in load capacitance processing system can improve in performance of the through and the rest of half power must be systems. The switching power and energy dissipation of static, dissipated as heat by a PMOS resistor in pull up network. In conventional CMOS circuits the energy is dissipated at completely restoring CMOS logic can be derived from the use of simple charge and energy conservation the time of the discharging process, which cannot be recovered 14. principle. Consider a CMOS logic design in Fig.1. Here, if pull-down network is on and pull-up network The energy dissipation can be reduced by computation of adiabatic logic family during the charging and is in cut-off region, the load capacitance (CL) at output is discharged through ground. Where if pull-down network discharging process, and some of the energy is reused by recycling from the CL. 1, 2, 14. is in cut-off region and the pull-up network is on then the Adiabatic logic families can be used to design low current will flow from supply of power to the load power memory components which further can be used in CL until the output reaches 2, 13. various applications 28. Adiabatic logic works with the energy recovery principle where all charge transfer occurs without any heat dissipation. In adiabatic logic the charging and Copyright © 2015 MECS I.J. Intelligent Systems and Applications, 2015, 08, 45-50 46 Design of Low Power Sequential Circuit by using Adiabatic Techniques discharging of load capacitance adiabatically is known as techniques have been implemented and discussed in this adiabatic switching 1, 2. The adiabatic charging paper. principle gives a way to charge load capacitor/parasitic In this paper: In Section II, operation and basic concept capacitors via a resistor without dissipating of ECRL and PFAL Adiabatic Logic are discussed. In Section III, a D flip- flop is described by using D- of energy 20. As shown in Fig.2. The adiabatic logic LATCH. Simulation results of inverter and D flip-flop are circuits utilize AC supply voltage instead of the DC supply voltage. shown in Section IV and Section V shows conclusion. II. OPERATION OF ECRL AND PFAL ADIABATIC LOGIC Adiabatic logic circuits manifest their efficiency in real applications. In adiabatic logic there are four phases, evaluate/pre-charge, hold, recovery and wait. Adiabatic circuits deliver energy in pre-charge phase and then recover it in the evaluation phase 1-4. In Fig.3 According to new method, the load capacitance gets Fig. 2. Adiabatic logic design charged (in evaluation phase) and discharged (in recovery phase) through a clock power by CMOS transmission In above circuit, the charge transferred is gate, and controlled by inputs. ECRL works on both (pre- and the average current will be (Q is charge and evaluation) phase simultaneously. Hold phase transferred charge to the load) so, the computed maintains the values (low and high) and then use these dissipated energy is 20. values as input for evaluation to next stage 4. (3) Here, EDISS = dissipated energy due to the charging time, = load capacitance, = power supply, 2 4 T = time of charging, 3 1 = ON resistance value of the PMOS, The energy dissipation (EDISS) is highly depended upon , so the energy dissipation can be reduced by minimizing the of PMOS network. The first order Fig. 3. Diagram of four phase logic for ECRL and PFAL approximation of is given as: 13, 20, 24. 1. Pre-charge phase/evaluate phase (4) 2. Hold phase 3. Recovery phase 4. Wait phase Where, U= mobility, A. Efficient Charge Adiabatic Logic = oxide capacitance, The proposed circuit of ECRL inverter gate uses the W= width, four phase clocking rule, the schematic and simulated waveform is shown in Fig.4 and Fig.5 simultaneously. L= length, The „evaluation/precharge phase‟ when input “a” is 1 = gate to source voltage, and inverterd input “ab” is 0, the clk varies from 0 to vdd then the output “out” will be at ground level and “outb” = threshold voltage, will follow the pck (power clock). As clk signal reaches to vdd, out and outb will enter The result due to the “adiabatic principle” is a very into „hold phase‟ (hold the logic value 0 and vdd slow change in systems which dissipate less energy than respectively). Now after the hold phase clk signal goes the fast ones; due to dissipation rates are proportional to from vdd to 0, the delivered value will recover and outb the rate of change 20. The equation (3) shows that it is returns its energy to clk in „recover phase‟. also possible to minimize the energy dissipation by ECRL uses 4-phase clock rule to recover all charges increasing the switching time values. delivered through the clk signal, the next stage should be This is known as the adiabatic charging principle and in the evaluation phase, if previous stage is holding the the “adiabatic” term we are using here to indicate that all valid phase 4, 14. transferred charge is occurring without generating the heat 2. The partially/quasi adiabatic ECRL and PFAL Copyright © 2015 MECS I.J. Intelligent Systems and Applications, 2015, 08, 45-50 Design of Low Power Sequential Circuit by using Adiabatic Techniques 47 Fig. 6. PFAL logic inverter Fig. 4. ECRL logic inverter Fig. 5. ECRL and PFAL inverter waveform and two CMOS transmission gate switches. Here, D is a B. Positive Feedback Adiabatic Logic single input. If ck is high then Q (output) will follow The proposed circuit of PFAL inverter gate is also value of the input D and when ck goes to zero, the Q or utilizes the 4-phase clock rule, the schematic and the information will preserve its state as the inverter loop. simulated waveforms are shown in Fig.6 and Fig.5 Hence, the ck input acts as a signal which allows data to simultaneously. be latched into the circuit when ck=1. During „evaluation phase‟ when input “a” is 1 and input bar “ab” is 0, the power clock “clk” goes from 0 to vdd then out will be at ground level and outb will follow the clk signal. As clk (Power Clock signal) reaches to vdd, out and outb will enter in „hold phase‟ (hold the logic value 0 and vdd respectively). Now after the hold phase clk signal goes from vdd to 0, the delivered will recover and outb returns its energy to clk „recover phase‟. Then „idle phase‟ will be inserted to manage the symmetry of clock, the authentic inputs are being produced in the wait stage. In wait phase, right inputs Fig. 7. CMOS D-LATCH arebeing prepared in last stage 5, 14. In Fig.7 this circuit is not an edge-triggered storage circuit because the final outcome depends on the input III. D FLIP-FLOP USING D-LATCH hence; the latch is transparent when ck is high. So this In digital circuit design there are various applications drawback makes it unsuitable for some applications like made by D-LATCH for temporary storage of data or as a counters. For removing this drawback considers a two delay element. Consider a conventional CMOS D- stage MASTER-SLAVE flip-flop circuit in Fig.8 which LATCH in Fig.7 which shows a basic two-inverter loop is designed by cascading two D-LATCH circuits. Copyright © 2015 MECS I.J. Intelligent Systems and Applications, 2015, 08, 45-50 48 Design of Low Power Sequential Circuit by using Adiabatic Techniques The master stage is driven by ck signal and slave stage sensitive, while master part is positive level-sensitive. is driven by ck signal. So, the slave part is negative level- Fig. 8. Edge-Triggered master-slave D flip-flop Fig. 9. simulated waveform of CMOS d flip-flop, ECRL and PFAL D flip-flop The power consumed by the ECRL inverter and PFAL inverter at various voltage power supplies ranging from IV. SIMULATION RESULTS 1.5V to 5V is plotted in Fig.10. The proposed sequential circuit D flip-flop is simulated ECRL D flip-flop and PFAL D flip-flop at various by the use of SPICE tool based on 90nm technology. For power supply variations form 0.9V to 1.2V is plotted in this simulation we have used W/L ratio for NMOS Fig.11. The result has been compared with conventional transistors is 135nm/90nm and for PMOS transistors it is CMOS circuit design. 405nm/90nm. Fig. 11. supply voltage vs power dissipation for a D FLIP-FLOP on Fig. 10. supply voltage vs power dissipation for an inverter at 90nm technology frequency=10MHz on 90nm technology Copyright © 2015 MECS I.J. Intelligent Systems and Applications, 2015, 08, 45-50 Design of Low Power Sequential Circuit by using Adiabatic Techniques 49 Here, it can be seen that in Fig.10 and Fig.11 the gap in Here, we can see that as frequency is increasing power between adiabatic logic families and CMOS logic is dissipation is reducing and at very high frequency again it reducing as supply voltage minimized. starts increase in power dissipation. Hence, it is Adiabatic logic families are strongly dependent on investigated that at high frequencies, the behavior is no parameters variation 17. Fig.12 and Fig.13 shows more adiabatic 13, 17. graphical representation of frequency versus dissipated But still PFAL and ECRL logic families consumes less power in traditional CMOS logic inverter and a power dissipation in circuit design by varying the sequential circuit D flip-flop at 1.5V and 1V power parameters in circuit. supply simultaneously. Adiabatic logic families show a advancement w.r.t For the comparison purpose the ECRL logic and PFAL CMOS, because of a high number of transistors needed in logic is compared by CMOS logic design at frequency adiabatic implementation comparatively by the traditional ranging from 0.1MHz to 1 kHz. CMOS implementation. V. CONCLUSION A D flip-flop circuit is designed with the help of inverter by using two adiabatic techniques ECRL, PFAL and a traditional CMOS have been successfully implemented to study the power consumption of digital and sequential circuits. The four phase clocking rule is used for to recover the efficient energy. The result has been carried out by using TSPICE simulation on 90nm Fig. 12. Frequency vs power dissipation for an inverter at VDD=1.5V technology files. It is investigated that PFAL and ECRL on 90nm technology logic are even a better energy saving techniques as traditional CMOS. It is found that at high frequency the behavior is no more adiabatic. In overall conclusion, adiabatic logic can be used for low power circuits in VLSI design which reduced the energy dissipation over traditional CMOS logic design circuits. ACKNOWLEDGEMENT The authors wish to thank to the ITM University for providing the EDA tools. RFERENCES Fig. 13. Frequency vs power dissipation for a D FLIP-FLOP at 1 J.S Denker, “A review of adiabatic computing,” in IEEE VDD=1V on 90nm technology Symp. On Low Power Electronics, pp.94-97, 1994. 2 William C. Athas, Lars “J.” Svensson, Member, IEEE, Table 1. Summary of the results for Fig.10 and Fig.11 Jeffrey G. Koller, Nestoras Tzartzanis, and Eric Ying-Chin D FLIP-FLOP Chou, Student Member, IEEE, “Low power digital system based on adiabatic-switching principles,” IEEE Trans. VDD CMOS ECRL PFAL VLSI Systems, vol.2, no.4, pp.398-407, Dec. 1994. (V) (u WATT) (u WATT) (u WATT) 3 A. Kramer, J. S. Denker, S. C. Avery, A. G. Dickinson, Frequency variation on Technology – 90nm at 1V and T. R. Wik, “Adiabatic computing with the 2N-2N2D 0.1MHz 5.187044 0.31157 0.370773 logic family,” in IEEE Symp. on VLSI Circuits Dig. of Tech. papers, pp. 25-26, Jun. 1994. 1MHz 19.23786 0.311697 0.487944 4 Y-Moon and D. K. Jeong, “An efficient charge recovery 10MHz 18.77796 0.157406 0.185722 logic circuits,” IEEE J. Solid-State Circuits, Vol.31, no.4, 100MHz 11.19761 0.157006 0.166279 pp.514-522, Apr. 1996. 5 A. Vetuli, S. Di Pascoli, and L. M. Reyneri, “Positive 1kHz 13.73116 0.79592 0.853199 feedback adiabatic logic,” Electronic Letters, vol.32, pp. Supply voltage variation on Technology – 90nm 1867-1869, Sept. 1996. 1.2 95530.18 0.132983 0.108913 6 Kramer, J. Denker, B. Flower and J. Moroney, “Second order adiabatic computation with 2N-2P and 2N-2N2P 1.1 39136.1 0.11151 0.089708 logic circuits,” Proceedings of international symposium on 1 27715.08 0.092326 0.0756 low power design, pp. 191-196, 1995. 0.9 19592.88 0.07461 0.06117 7 Blotti, S. D. Pascoli, R. Saletti, and D. S. Landsiedel, “Sample model for positive feedback adiabatic logic power 0.8 9678.32 0.059086 0.048556 Copyright © 2015 MECS I.J. Intelligent Systems and Applications, 2015, 08, 45-50 50 Design of Low Power Sequential Circuit by using Adiabatic Techniques consumption estimation,” Electronics Letters, vol.36, no. 2, 24 A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, pp. 116-118, Jan. 2000. “Low-power CMOS digital design,” in IEEE Journal 8 Blotti, S. D. Pascoli, R. Saletti, and D. S. Landsiedel, Solid- State Circ., vol. 27, no. 4, pp. 473-484, April 1992. “Improving the positive feedback adiabatic logic family,” 25 R. T. Hinman and M. F. Schlecht, “Power dissipation in Advances in Radio Science, pp. 221-225, 2004. measurements on recovered energy logic,” in IEEE Symp. 9 K. Lo and P. C. H. Chan, “An adiabatic differential logic On VLSI Circuits Dig. Of tech. Papers, pp. 19-20, June for low power digital systems,” IEEE Trans. Circuits Syst. 1994. II, vol. 46, pp. 1245-1250, Sept. 1999. 26 L. G. Heller and W. R. Griffin, “Cascode voltage switch 10 V. G. Oklobdzija, D. Maksimovic, L. Fengcheng, “Pass- logic: A differential CMOS logic family,” in ISSCC Dig. transistor adiabatic logic using single power-clock supply,” Tech. Papers, pp. 16-17, 1984. IEEE Trans. Circ. Syst. II, vol. 44, pp. 842-846, Oct. 1997. 27 Mohammad Gholami, Gholamreza Ardeshir, H. Miar- 11 W. C. Athas, J. G. Koller, and L. J. Svensson, “An energy- Naimi, “A noise and mismatches of delay cells and their efficient CMOS line driver using adiabatic switching,” effects on DLLs,” in IJISA, Vol. 6, No. 5, pp. 37-43, April Proceeding Fourth Great Lakes Symp. VLSI Design, pp. 2014. 196-199, Mar. 1994. 28 Sanjay Singh, Ravi Saini, Anil K. Saini, AS Mandal, 12 T. Indermauer and M. Horowitz, “Evaluation of charge Chandra Shekhar, “Performance evaluation of different recovery circuits and adiabatic switching for low power memory components for FPGA based embedded system design,” Technical Digest IEEE Sym. Low Power design for video processing application,” in IJISA, Vol. 5, Electronics, San Diego, pp. 102-103, Oct. 2002. No. 12, Nov. 2013. 13 Shweta Chauhan, Deepesh Ranka, Kamlesh Yadav, 29 Ch. Praveen Kumar, S. K. Tripathy, Rajeev Tripathi, “High Rakesh Kumar Yadav, Ashwani K. Rana, “Four phase Performance Sequential Circuits with Adiabatic clocking rule for energy efficient digital circuits- an Complementary Pass-Transistor Logic (ACPL) ,” in adiabatic concept ,” International Conference on Computer TENCON 2009, IEEE, pp. 1-4. and Communication Technology (ICCCT), pp. 209-214, 30 Moshe Avital, Hadar dagan, Itamar Levi, Osnat Keren, and IEEE, 2011. Alexander Fish, “DPA-Secured Quasi-Adiabatic Logic 14 Rakesh Kumar Yadav, Ashwani K. Rana, Shweta Chauhan, (SQAL) for Low-Pwer Passaive RFID Tags Emplying S- “Adiabatic technique for energy efficient logic circuits Boxes” in IEEE transaction on circuits and systems, Vol. design,” Procceding of ICETECT, pp. 776-780, IEEE, 62, No.1, pp. 149-156,January 2015. 2011. 31 Yango Wu, Weijiang Zhang, and Jianping Hu, “Adiabatic 15 Ashmeet Kaur Bakshi, Manoj Sharma, “Design of basic 4-2 Compressors for Low-Power Multiplier” in IEEE gates using ECRL and PFAL,” International Conf. on Circuits and Systems, Vol. 2, pp. 1473-1476. Computer and Communication Technology (ICCCT), pp. 32 Abhishek Agal. Pardeep, Bal Krishan, “comparative 580-585, IEEE, 2013. analysis of various SRAM cells with low power, high read 16 Atul Kumar Maurya, Gagnesh Kumar, “Adiabatic logic: stability and low area” in IJEM, Vol. 4, No. 3, pp. 1-12, energy efficient technique for VLSI applications,” December 2014. International Conf. on Computer and Communication Technology (ICCCT), pp. 234-238, IEEE, 2011. 17 Ettore Amirante, Agnese Bargagli-Stffi, Jurgen Fischer, Authors’ Profiles Giueppe Iannaccone, and Doris Schmitt Landsiedel, Charu rana was born in Itanagar, “Variations of the power dissipation in adiabatic logic Arunachal Pradesh on 1984. She recieved gates,” in Proc. 11th Int. Workshop PATMOS, Yverdon- her B.Tech degree in Electronics and Les-Bains, Switzerland, pp. 9.1.1-10, Sept. 2001. Communication Engineering from 18 M. Eisele, J. Berthold, D. S. Landsiedel, R. Mahnkopf, Kurukshetra University in 2005 and “The Impact of Intra-Die Device Parameter Variations on M.Tech in VLSI Design from Mody Path Delays and on the Design for Yield of Low Voltage Instiute of Technology and Science, Sikar Digital Circuits,” IEEE Transactions on VLSI Systems, in 2008. She is currently involved in Ph.D Vol. 5, No. 4, pp. 360-368, Dec. 1997. work in Jamia Millia Islamia. Her area of research is Low 19 R. T. Hinman and M. F. Schlecht, “Power dissipation Power Design Techniques. She is currently working as measurements on recovered energy logic,” in IEEE Symp. Assistant Professor, Senior Scale in ITM University, Gurgaon, VLSI Circuits Dig. Tech. Papers, pp. 19–20, June 1994. Haryana, India. 20 J. G Koller, W. C. Athas, “Adiabatic switching, low enrgy computing, and the physics of storing and erasing information,” in Physics and Computation, pp. 267-270, Priyanka Ojha was born in Hisar, Oct. 1992. Haryana, India on September 2, 1989. 21 Reginald H. Vanlalchaka, Soumik Roy, “Power eifficient She received the B.Tech degree from odd parity generator and checker,” in Emerging Trends and Kurukshetra University in 2013. She is Applications in Computer Science, pp. 65-69, Sept. 2013. currently involved in M.Tech work in 22 Dr. D. Somasundareswari, A. K. Kumar, Dr. D. Duraisamy, ITM University. Her area of research is G. Sabarinathan, “Asynchronous design of energy efficient Low Power Design Techniques. full adder,” in International Conference on Computer Communication and Informatics, pp. 1-6, Jan. 2013. 23 V. S. Kanchana Bhaaskaran, “Asymmertical positive feedback adiabatic logic for low power and higher frequency,” in International Conference on Advances in Recent Technologies in Communication and Computing, pp. 5-9, Oct. 2010. Copyright © 2015 MECS I.J. Intelligent Systems and Applications, 2015, 08, 45-50

Advise: Why You Wasting Money in Costly SEO Tools, Use World's Best Free SEO Tool Ubersuggest.