Solution Manual of Computer system Architecture

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SOLUTION MANUAL OF COMPUTER ORGANIZATION BY CARL HAMACHER, ZVONKO VRANESIC & SAFWAT ZAKY Chapter 1 Basic Structure of Computers 1.1.  Transfer the contents of register PC to register MAR  Issue a Read command to memory, and then wait until it has transferred the requested word into register MDR  Transfer the instruction from MDR into IR and decode it  Transfer the address LOCA from IR to MAR  Issue a Read command and wait until MDR is loaded  Transfer contents of MDR to the ALU  Transfer contents of R0 to the ALU  Perform addition of the two operands in the ALU and transfer result into R0  Transfer contents of PC to ALU  Add 1 to operand in ALU and transfer incremented address to PC 1.2.  First three steps are the same as in Problem 1.1  Transfer contents of R1 and R2 to the ALU  Perform addition of two operands in the ALU and transfer answer into R3  Last two steps are the same as in Problem 1.1 1.3. (a) Load A,R0 Load B,R1 Add R0,R1 Store R1,C _ _ (b) Yes; Move B,C Add A,C 1.4. (a) Non-overlapped time for Program i is 19 time units composed as: Program i 1 3 1 2 1 3 1 2 1 3 1 input compute output 1 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/_ _ Overlapped time is composed as: Program i - 1 1 3 1 output 15 time units Program i 1 3 1 9 1 3 1 input compute output Program i+1 1 3 1 input Time between successive program completions in the overlapped case is 15 time units, while in the non-overlapped case it is 19 time units. Therefore, the ratio is 15/19. (b) In the discussion in Section 1.5, the overlap was only between input and output of two successive tasks. If it is possible to do output from job i 1, compute for job i, and input to job i+1 at the same time, involving all three units of printer, processor, and disk continuously, then potentially the ratio could be reduced toward 1/3. The OS routines needed to coordinate multiple unit activity cannot be fully overlapped with other activity because they use the processor. Therefore, the ratio cannot actually be reduced to 1/3. 1.5. (a) Let T = (N  S )=R and T = (N  S )=R be execution times R R R R C C C C on the RISC and CISC processors, respectively. Equating execution times and clock rates, we have 1:2N = 1:5N R C Then N =N = 1:2=1:5 = 0:8 C R Therefore, the largest allowable value for N is 80% of N . C R 2 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/(b) In this case 1:2N =1:15 = 1:5N =1:00 R C Then N =N = 1:2=(1:15 1:5) = 0:696 C R Therefore, the largest allowable value for N is 69.6% of N . C R 1.6. (a) Let cache access time be 1 and main memory access time be 20. Every instruction that is executed must be fetched from the cache, and an additional fetch from the main memory must be performed for 4% of these cache accesses. Therefore, 1:0 20 Speedup factor = = 11:1 (1:0 1) + (0:04 20) (b) 1:0 20 Speedup factor = = 16:7 (1:0 1) + (0:02 20) 3 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/Chapter 2 Machine Instructions and Programs 2.1. The three binary representations are given as: Decimal Sign-and-magnitude 1's-complement 2's-complement values representation representation representation 5 0000101 0000101 0000101 2 1000010 1111101 1111110 14 0001110 0001110 0001110 10 1001010 1110101 1110110 26 0011010 0011010 0011010 19 1010011 1101100 1101101 51 0110011 0110011 0110011 43 1101011 1010100 1010101 2.2. (a) (a) 00101 (b) 00111 (c) 10010 + 01010 + 01101 + 01011 01111 10100 11101 no over ow over ow no over ow (d) 11011 (e) 11101 (f) 10110 + 00111 + 11000 + 10011 00010 10101 01001 no over ow no over ow over ow (b) To subtract the second number, form its 2's-complement and add it to the rst number. (a) 00101 (b) 00111 (c) 10010 + 10110 + 10011 + 10101 11011 11010 00111 no over ow no over ow over ow (d) 11011 (e) 11101 (f) 10110 + 11001 + 01000 + 01101 10100 00101 00011 no over ow no over ow no over ow 1 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/2.3. No; any binary pattern can be interpreted as a number or as an instruction. 2.4. The number 44 and the ASCII punctuation character \comma". 2.5. Byte contents in hex, starting at location 1000, will be 4A, 6F, 68, 6E, 73, 6F, 6E. The two words at 1000 and 1004 will be 4A6F686E and 736F6EXX. Byte 1007 (shown as XX) is unchanged. (See Section 2.6.3 for hex nota- tion.) 2.6. Byte contents in hex, starting at location 1000, will be 4A, 6F, 68, 6E, 73, 6F, 6E. The two words at 1000 and 1004 will be 6E686F4A and XX6E6F73. Byte 1007 (shown as XX) is unchanged. (See section 2.6.3 for hex nota- tion.) 2.7. Clear the high-order 4 bits of each byte to 0000. 2.8. A program for the expression is: Load A Multiply B Store RESULT Load C Multiply D Add RESULT Store RESULT 2 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/2.9. Memory word location J contains the number of tests, j, and memory word location N contains the number of students, n. The list of student marks begins at memory word location LIST in the format shown in Figure 2.14. The parameter Stride = 4(j + 1) is the distance in bytes between scores on a particular test for adjacent students in the list. The Base with index addressing mode (R1,R2) is used to access the scores on a particular test. Register R1 points to the test score for student 1, and R2 is incremented by Stride in the inner loop to access scores on the same test by successive students in the list. Move J,R4 Compute and place Stride = 4(j + 1) Increment R4 into register R4. Multiply 4,R4 Move LIST,R1 Initialize base register R1 to the Add 4,R1 location of the test 1 score for student 1. Move SUM,R3 Initialize register R3 to the location of the sum for test 1. Move J,R10 Initialize outer loop counter R10 to j. OUTER Move N,R11 Initialize inner loop counter R11 to n. Clear R2 Clear index register R2 to zero. Clear R0 Clear sum register R0 to zero. INNER Add (R1,R2),R0 Accumulate the sum of test scores in R0. Add R4,R2 Increment index register R2 by Stride value. Decrement R11 Check if all student scores on current Branch0 INNER test have been accumulated. Move R0,(R3) Store sum of current test scores and Add 4,R3 increment sum location pointer. Add 4,R1 Increment base register to next test score for student 1. Decrement R10 Check if the sums for all tests have Branch0 OUTER been computed. 3 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/2.10. (a) Memory accesses Move AVEC,R1 1 Move BVEC,R2 1 Load N,R3 2 Clear R0 1 LOOP Load (R1)+,R4 2 Load (R2)+,R5 2 Multiply R4,R5 1 Add R5,R0 1 Decrement R3 1 Branch0 LOOP 1 Store R0,DOTPROD 2 (b) k = 1 + 1 + 2 + 1 + 2 = 7; and k = 2 + 2 + 1 + 1 + 1 + 1 = 8 1 2 2.11. (a) The original program in Figure 2.33 is ecient on this task. (b) k = 7; and k = 7 1 2 This is only better than the program in Problem 2.10(a) by a small amount. 2.12. The dot product program in Figure 2.33 uses ve registers. Instead of using R0 to accumulate the sum, the sum can be accumulated directly into DOTPROD. This means that the last Move instruction in the program can be removed, but DOTPROD is read and written on each pass through the loop, signi cantly increasing memory accesses. The four registers R1, R2, R3, and R4, are still needed to make this program ecient, and they are all used in the loop. Suppose that R1 and R2 are retained as pointers to the A and B vectors. Counter register R3 and temporary storage register R4 could be replaced by memory locations in a 2-register machine; but the number of memory accesses would increase signi cantly. 2.13. 1220, part of the instruction, 5830, 4599, 1200. 4 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/2.14. Linked list version of the student test scores program: Move 1000,R0 Clear R1 Clear R2 Clear R3 LOOP Add 8(R0),R1 Add 12(R0),R2 Add 16(R0),R3 Move 4(R0),R0 Branch0 LOOP Move R1,SUM1 Move R2,SUM2 Move R3,SUM3 2.15. Assume that the subroutine can change the contents of any register used to pass parameters. Subroutine Move R5,(SP) Save R5 on stack. Multiply 4,R4 Use R4 to contain distance in bytes (Stride) between successive elements in a column. Multiply 4,R1 Byte distances from A(0,0) Multiply 4,R2 to A(0,x) and A(0,y) placed in R1 and R2. LOOP Move (R0,R1),R5 Add corresponding Add R5,(R0,R2) column elements. Add R4,R1 Increment column element Add R4,R2 pointers by Stride value. Decrement R3 Repeat until all Branch0 LOOP elements are added. Move (SP)+,R5 Restore R5. Return Return to calling program. 5 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/2.16. The assembler directives ORIGIN and DATAWORD cause the object pro- gram memory image constructed by the assembler to indicate that 300 is to be placed at memory word location 1000 at the time the program is loaded into memory prior to execution. The Move instruction places 300 into memory word location 1000 when the instruction is executed as part of a program. 2.17. (a) Move (R5)+,R0 Add (R5)+,R0 Move R0,(R5) (b) Move 16(R5),R3 (c) Add 40,R5 6 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/2.18. (a) Wraparound must be used. That is, the next item must be entered at the beginning of the memory region, assuming that location is empty. (b) A current queue of bytes is shown in the memory region from byte location 1 to byte location k in the following diagram. Increasing addresses Current queue 1 of bytes k . . . . . . OUT IN The IN pointer points to the location where the next byte will be appended to the queue. If the queue is not full with k bytes, this location is empty, as shown in the diagram. The OUT pointer points to the location containing the next byte to be removed from the queue. If the queue is not empty, this location contains a valid byte, as shown in the diagram. Initially, the queue is empty and both IN and OUT point to location 1. (c) Initially, as stated in Part b, when the queue is empty, both the IN and OUT pointers point to location 1. When the queue has been lled with k bytes and none of them have been removed, the OUT pointer still points to location 1. But the IN pointer must also be pointing to location 1, because (following the wraparound rule) it must point to the location where the next byte will be appended. Thus, in both cases, both pointers point to location 1; but in one case the queue is empty, and in the other case it is full. (d) One way to resolve the problem in Part (c) is to maintain at least one empty location at all times. That is, an item cannot be appended to the queue if (IN + 1) Modulo k = OUT. If this is done, the queue is empty only when IN = OUT. (e) Append operation:  LOC IN  IN (IN + 1) Modulo k  If IN = OUT, queue is full. Restore contents of IN to contents of LOC and indicate failed append operation, that is, indicate that the queue was full. Otherwise, store new item at LOC. 7 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/ Remove operation:  If IN = OUT, the queue is empty. Indicate failed remove operation, that is, indicate that the queue was empty. Otherwise, read the item pointed to by OUT and perform OUT (OUT + 1) Modulo k. 2.19. Use the following register assignment: R0 Item to be appended to or removed from queue R1 IN pointer R2 OUT pointer R3 Address of beginning of queue area in memory R4 Address of end of queue area in memory R5 Temporary storage for IN during append operation Assume that the queue is initially empty, with R1 = R2 = R3. The following APPEND and REMOVE routines implement the proce- dures required in Part (e) of Problem 2.18. APPEND routine: Move R1,R5 Increment R1 Increment IN pointer Compare R1,R4 Modulo k. Branch0 CHECK Move R3,R1 CHECK Compare R1,R2 Check if queue is full. Branch=0 FULL MoveByte R0,(R5) If queue not full, append item. Branch CONTINUE FULL Move R5,R1 Restore IN pointer and send Call QUEUEFULL message that queue is full. CONTINUE ::: REMOVE routine: Compare R1,R2 Check if queue is empty. Branch=0 EMPTY If empty, send message. MoveByte (R2)+,R0 Otherwise, remove byte and Compare R2,R4 increment R2 Modulo k. Branch0 CONTINUE Move R3,R2 Branch CONTINUE EMPTY Call QUEUEEMPTY CONTINUE ::: 8 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/2.20. (a) Neither nesting nor recursion are supported. (b) Nesting is supported, because di erent Call instructions will save the return address at di erent memory locations. Recursion is not supported. (c) Both nesting and recursion are supported. 2.21. To allow nesting, the rst action performed by the subroutine is to save the contents of the link register on a stack. The Return instruction pops this value into the program counter. This supports recursion, that is, when the subroutine calls itself. 2.22. Assume that register SP is used as the stack pointer and that the stack grows toward lower addresses. Also assume that the memory is byte- addressable and that all stack entries are 4-byte words. Initially, the stack is empty. Therefore, SP contains the address LOWERLIMIT + 4. The routines CALLSUB and RETRN must check for the stack full and stack empty cases as shown in Parts (b) and (a) of Figure 2.23, respectively. CALLSUB Compare UPPERLIMIT,SP Branch0 FULLERROR Move RL,(SP) Branch (R1) RETRN Compare LOWERLIMIT,SP Branch0 EMPTYERROR Move (SP)+,PC 2.23. If the ID of the new record matches the ID of the Head record of the current list, the new record will be inserted as the new Head. If the ID of the new record matches the ID of a later record in the current list, the new record will be inserted immediately after that record, including the case where the matching record is the Tail record. In this latter case, the new record becomes the new Tail record. Modify Figure 2.37 as follows:  Add the following instruction as the rst instruction of the subrou- tine: INSERTION Move 0, ERROR Anticipate successful insertion of the new record. Compare 0, RHEAD (Existing instruction.) 9 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/ After the second Compare instruction, insert the following three in- structions: Branch6=0 CONTINUE1 Three new instructions. Move RHEAD, ERROR Return CONTINUE1 Branch0 SEARCH (Existing instruction.)  After the fourth Compare instruction, insert the following three in- structions: Branch6=0 CONTINUE2 Three new instructions. Move RNEXT, ERROR Return CONTINUE2 Branch0 INSERT (Existing instruction.) 2.24. If the list is empty, the result is unpredictable because the rst instruction will compare the ID of the new record to the contents of memory location zero. If the list is not empty, the following happens. If the contents of RIDNUM are less than the ID number of the Head record, the Head record will be deleted. Otherwise, the routine loops until register RCURRENT points to the Tail record. Then RNEXT gets loaded with zero by the instruction at LOOP, and the result is unpredictable. Replace Figure 2.38 with the following code: DELETION Compare 0, RHEAD If the list is empty, Branch=0 6 CHECKHEAD return with RIDNUM unchanged. Return CHECKHEAD Compare (RHEAD), RIDNUM Check if Head record Branch=0 6 CONTINUE1 is to be deleted and Move 4(RHEAD), RHEAD perform deletion if it Move 0, RIDNUM is, returning with zero Return in RIDNUM. CONTINUE1 Move RHEAD, RCURRENT Otherwise, continue searching. LOOP Move 4(CURRENT), RNEXT Compare 0, RNEXT If all records checked, Branch=0 6 CHECKNEXT return with IDNUM unchanged. Return CHECKNEXT Compare (RNEXT), RIDNUM Check if next record is Branch=0 6 CONTINUE2 to be deleted and perform Move 4(RNEXT), RTEMP deletion if it is, Move RTEMP, 4(RCURRENT) returning with zero Move 0, RIDNUM in RIDNUM. Return CONTINUE2 Move RNEXT, RCURRENT Otherwise, continue Branch LOOP the search. 10 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/Chapter 3 ARM, Motorola, and Intel Instruction Sets PART I: ARM 3.1. (a) R8, R9, and R10, contain 1, 2, and 3, respectively. (b) The values 20 and 30 are pushed onto a stack pointed to by R1 by the two Store instructions, and they occupy memory locations 1996 and 1992, respectively. They are then popped o the stack into R8 and R9. Finally, the Subtract instruction results in 10 (30 20) being stored in R10. The stack pointer R1 is returned to its original value of 2000. (c) The numbers in memory locations 1016 and 1020 are loaded into R4 and R5, respectively. These two numbers are then added and the sum is placed in register R4. The nal address value in R2 is 1024. 3.2. (b) A memory operand cannot be referenced in a Subtract instruction. (d) The immediate value 257 is 100000001 in binary, and is thus too long to t in the 8-bit immediate eld. Note that it cannot be generated by the rotation of any 8-bit value. 3.3. The following two instructions perform the desired operation: MOV R0,R0,LSL 24 MOV R0,R0,ASR 24 3.4. Use register R0 as a counter register and R1 as a work register. MOV R0,32 Load R0 with count value 32. MOV R1,0 Clear register R1 to zero. LOOP MOV R2,R2,LSL 1 Shift contents of R2 left one bit position, moving the high-order bit into the C ag. MOV R1,R1,RRX Rotate R1 right one bit position, including the C ag, as shown in Figure 2.32d. SUBS R0,R0,1 Check if nished. BGT LOOP MOV R2,R1 Load reversed pattern back into R2. 1 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/3.5. Program trace: TIME R0 R1 R2 after 1st execution of BGT 3 4 NUM1 + 4 after 2nd execution of BGT 14 3 NUM1 + 8 after 3rd execution of BGT 13 2 NUM1 + 12 3.6. Assume bytes are unsigned 8-bit values. LDR R0,N R0 is list counter ADR R1,X R1 points to X list ADR R2,Y R2 points to Y list ADR R3,LARGER R3 points to LARGER list LOOP LDRB R4,R1,1 Load X list byte into R4 LDRB R5,R2,1 Load Y list byte into R5 CMP R4,R5 Compare bytes STRHSB R4,R3,1 Store X byte if larger or same STRLOB R5,R3,1 Store Y byte if larger SUBS R0,R0,1 Check if nished BGT LOOP 3.7. The inner loop checks for a match at each possible position. LDR R0,N Compute outer loop count LDR R1,M and store in R2. SUB R2,R0,R1 ADD R2,R2,1 ADR R3,STRING Use R3 and R4 as base ADR R4,SUBSTRING pointers for each match. OUTER MOV R5,R3 Use R5 and R6 as running MOV R6,R4 pointers for each match. LDR R7,M Initialize inner loop counter. INNER LDRB R0,R5,1 Compare bytes. LDRB R1,R6,1 CMP R0,R1 BNE NOMATCH If not equal, go next. SUBS R7,R7,1 Check if all bytes compared. BGT INNER MOV R0,R3 If substring matches, load B NEXT its position into R0 and exit. NOMATCH ADD R3,R3,1 Go to next substring. SUBS R2,R2,1 Check if all positions tried. BGT OUTER MOV R0,0 If yes, load zero into NEXT ::: R0 and exit. 2 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/3.8. This solution assumes that the last number in the series of n numbers can be represented in a 32-bit word, and that n 2. MOV R0,N Use R0 to count numbers SUB R0,R0,2 generated after 1. ADR R1,MEMLOC Use R1 as memory pointer. MOV R2,0 Store rst two numbers, STR R2,R1,4 0 and 1, from R2 MOV R3,1 and R3 into memory. STR R3,R1,4 LOOP ADD R3,R2,R3 Starting with number i 1 STR R3,R1,4 in R2 and i in R3, compute and place i + 1 in R3 and store in memory. SUB R2,R3,R2 Recover old i and place in R2. SUBS R0,R0,1 Check if all numbers BGT LOOP have been computed. 3.9. Let R0 point to the ASCII word beginning at location WORD. To change to uppercase, we need to change bit b from 1 to 0. 5 NEXT LDRB R1,R0 Get character. CMP &20,R1 Check if space character. ANDNE &DF,R1 If not space: clear STRNEB R1,R0,1 bit 5, store BNE NEXT converted character, get next character. 3 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/3.10. Memory word location J contains the number of tests, j, and memory word location N contains the number of students, n. The list of student marks begins at memory word location LIST in the format shown in Figure 2.14. The parameter Stride = 4(j + 1) is the distance in bytes between scores on a particular test for adjacent students in the list. The Post-indexed addressing mode R2,R3,LSL 2 is used to access the successive scores on a particular test in the inner loop. The value in register R2 before each entry to the inner loop is the address of the score on a particular test for the rst student. Register R3 contains the value j + 1. Therefore, register R2 is incremented by the Stride parameter on each pass through the inner loop. LDR R3,J Load j + 1 into R3 to ADD R3,R3,1 be used as an address o set. ADR R4,SUM Initialize R4 to the sum location for test 1. ADR R5,LIST Load address of test 1 score ADD R5,R5,4 for student 1 into R5. LDR R6,J Initialize outer loop counter R6 to j. OUTER LDR R7,N Initialize inner loop counter R7 to n. MOV R2,R5 Initialize base register R2 to location of student 1 test score for next inner loop sum computation. MOV R0,0 Clear sum accumulator register R0. INNER LDR R1,R2,R3,LSL 2 Load test score into R1 and increment R2 by Stride to point to next test score. ADD R0,R0,R1 Accumulate score into R0. SUBS R7,R7,1 Check if all student scores BGT INNER for current test are added. STR R0,R4,4 Store sum in memory. ADD R5,R5,4 Increment R5 to next test score for student 1. SUBS R6,R6,1 Check if sums for all test BGT OUTER scores have been accumulated. 4 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/3.11. Assume that the subroutine can change the contents of any registers used to pass parameters. STR R5,R13,4 Save R5 on stack. ADD R1,R0,R1,LSL 2 Load address of A(0,x) into R1. ADD R2,R0,R2,LSL 2 Load address of A(0,y) into R2. LOOP LDR R5,R1,R4,LSL 2 Load A(i,x) into R5 and increment pointer R1 by Stride = 4m. LDR R0,R2 Load A(i,y) into R0. ADD R0,R0,R5 Add corresponding column entries. STR R0,R2,R4,LSL 2 Store sum in A(i,y) and increment pointer R2 by Stride. SUBS R3,R3,1 Repeat loop until all BGT LOOP entries have been added. LDR R5,R13,4 Restore R5 from stack. MOV R15,R14 Return. 3.12. This program is similar to Figure 3.9, and makes the same assumptions about register usage and status word bit locations. LDR R0,N Use R0 as the loop counter for reading n characters. READ LDR R3,R1 Load INSTATUS and TST R3,8 wait for character. BEQ READ LDRB R3,R1,4 Read character and push STRB R3,R6,1 onto stack. ECHO LDR R4,R2 Load OUTSTATUS and TST R4,8 wait for display. BEQ ECHO STRB R3,R2,4 Send character to display. SUBS R0,R0,1 Repeat until n BGT READ characters read. 3.13. Assume that most of the time between successive characters being struck is spent in the three-instruction wait loop that starts at location READ. The BEQ READ instruction is executed once every 60 ns while 9 8 this loop is being executed. There are 10 =10 = 10 ns between succes- sive characters. Therefore, the BEQ READ instruction is executed 8 6 10 =60 = 1:6666 10 times per character entered. 5 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/3.14. Main Program READLINE BL GETCHAR Call character read subroutine. STRB R3,R0,1 Store character in memory. BL PUTCHAR Call character display subroutine. TEQ R3,CR Check for end-of-line character. BNE READLINE Subroutine GETCHAR GETCHAR LDR R3,R1 Wait for character. TST R3,8 BEQ GETCHAR LDRB R3,R1,4 Load character into R3. MOV R15,R14 Return. Subroutine PUTCHAR PUTCHAR STMFD R13,fR4,R14g Save R4 and Link register. DISPLAY LDR R4,R2 Wait for display. TST R4,8 BEQ DISPLAY STRB R3,R2,4 Send character to display. LDMFD R13,fR4,R15g Restore R4 and Return. 6 For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/