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Microprocessor and Microcontroller

Microprocessor and Microcontroller 4
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Published Date:12-07-2017
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A Course Material on Microprocessor and Microcontroller By Ms. M. NIVETHA ASSISTANT PROFESSOR DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING SASURIE COLLEGE OF ENGINEERING VIJAYAMANGALAM – 638 056 UNIT I 8085 PROCESSOR 1) 8085 Architecture: The architecture of 8085 consist various components like: 1. Accumulator & Register sets. 2. Program counter and stack pointer. 3. Flag Register. 4. ALU. 5. Instruction decoder and machine cycle encoder. 6. Address buffer. 7. Address/data buffer. 8. Increment/Decrement latch. 9. Interrupt control. 10. Serial I/O like SOD,SID. 11. Timing and Control circuit. Accumulator: • The accumulator is an 8-bit register then is part of the arithmetic/logic unit(ALU). • This register is used to store to store 8-bit data this data is used to perform arithmetic & logical operation. • The result of an operation is stored in the accumulator. • The accumulator is also identified as register A. • The accumulator is used for data transfer between an I/O port and memory location. Registersets: • The 8085 simulator has six general-purpose registers to store 8-bit data; these are identified as B, C, D, E, H and L. They can be combined as register pair likeBC, DE and HL – to perform some 16-bit operations. • The programmer can use these registers to store or copy data into the registers by using data copy instructions. • Out of these six registers, four 8-bit registers are scratch pad registers which are accessible to the programmer and hence can be used to temporarily store data during a program execution. • And the two registers H and L are utilized in indirect addressing mode. In this mode, the memory location i.e. the address is specified by the contents of the registers. Program Counter (PC): • 16 bit register which holds the memory address of the next instruction to be executed in the next step. • This 16-bit register deals with sequencing the execution of instructions. This register is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register. • The microprocessor uses this register to sequence the execution of the instructions. The function of the program counter is to point to the memory address from which the next instruction is to be fetched. When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location. Stack Pointer (SP): • Stack pointer is used during subroutine calling and execution. • The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory location in R/W memory, called the stack. Flag or status register: • The ALU includes five flip-flops, which are set or reset after an operation according to data conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. • The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data conditions. • For example, after an addition of two numbers, if the sum in the accumulator is larger than eight bits, the flip-flop uses to indicate a carry called the Carry flag (CY) is set to one. • When an arithmetic operation results is zero, the flip-flop called the Zero(Z) flag is set to one. • The Figure shows an 8-bit register, called the flag register, adjacent to the accumulator.. • Flag is an 8-bit register containing 5no.s of 1-bit flags: 1. Sign - If the result of the latest arithmetic operation is having MSB (most- significant bit) „1‟ (meaning it is a negative number), then the sign flag is set. Otherwise, it is reset to „0‟ which means it is a positive number. 2. Zero - If the result of the latest operation is zero, then zero flag will be set; otherwise it be reset. 3. Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result. 4. Parity - set if the parity (the number of set bits in the result) is even. i.e., If the result of the latest operation is having even number of „1‟s, then this flag will be set. Otherwise this will be reset to „0‟. This is used for error checking. 5. Carry - set if there was a carry during addition, or borrow during subtraction/comparison. Otherwise it will be reset. Instruction register or Decoder:- • Instruction register holds the instruction that is currently being processed. • Once the instruction is fetch from the memory, it is reloaded in the instruction register for some time, after the decoder decode the instruction performing some event or task. Address buffer: • The remaining higher order address lines form the address buffer ranging fromA15-A8.This is having the unidirectional buffer Address/data buffer: • The address bus will be having 16 address linesA15-A0 .In which A7-A0 are called as lower addressing lines and these are multiplexed with data linesD7-D0 to form multiplexed address /data buffer .The address/data buffer is the bidirectional bus. Increment/Decrement Address Latch: • It increments/ decrements the address before sent to the address buffer Interrupts: The processor has 5 interrupts. They are presented below in the order of theirpriority (from lowest to highest): • INTR is maskable 8080A compatible interrupt. When the interrupt occurs, the processor fetches from the bus one instruction, usually one of these instructions: One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and branches to memory location N 8 (where N is a 3- bit number from 0 to 7 supplied with the RST instruction). • CALL instruction (3 byte instruction). The processor calls the subroutine, address of which is specified in the second and third bytes of the instruction. • RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 2CH (hexadecimal) address. • RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 34H (hexadecimal) address. • RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 3CH (hexadecimal) address. • TRAP is a non-maskable interrupt. When this interrupt is received the processorsaves the contents of the PC register into stack and branches to 24H (hexadecimal) address. • All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM Instruction Serial I/O control • There are control signals used for controlling 8085 these are subdivided into 2 types: 1. SID(serial input data): This is used for transferring of data into the memory serially. 2. SOD(serial output data): This is used for transferring of data from memory to external devices • Interrupt control is used to transfer the ISR to the CPU. 2) PIN DIAGRAM Timing and Control Unit: • The timing and control unit accepts information from the instruction decoder andgenerates different control signal. This unit synchronizes all the microprocessor operation and generates control and status signal necessary for communication between the microprocessor and peripherals. A8 - A15 (Output 3 State): Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/0 address,3 stated during Hold and Halt modes. AD0 - AD7 (Input / Output 3 state):  Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on the bus during the first clock cycle of a machine state.  It then becomes the data bus during the second and third clock cycles. 3 stated during Hold and Halt modes. ALE (Output):  Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals.  The falling edge of ALE is set to guarantee setup and hold times for the address information. ALE can also be used to strobe the status information. ALE is never 3stated. SO, S1 (Output): Data Bus Status. Encoded status of the bus cycle: S1 S0 0 0 HALT 0 1 WRITE 1 0 READ 1 1 FETCH S1 can be used as an advanced R/W status. RD (Output 3state): READ: indicates the selected memory or I/0 device is to be read and that the Data Bus is available for the data transfer. WR (Output 3state):  WRITE: indicates the data on the Data Bus is to be written into the selected memory or I/0location.  Data is set up at the trailing edge of WR. 3stated during Hold and Halt modes. READY (Input):  If Ready is high during a read or write cycle, it indicates that the memory or peripheral is readyto send or receive data.  If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle. HOLD (Input):  HOLD: indicates that another Master is requesting the use of the Address and Data Buses.  The CPU, upon receiving the Hold request will relinquish the use of buses as soon as the completion of the current machine cycle.  Internal processing can continue. The processor can regain the buses only after the Hold is removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated. HLDA (Output):  HOLD ACKNOWLEDGE: indicates that the CPU has received the Hold request and that it willrelinquish the buses in the next clock cycle.  HLDA goes low after the Hold request is removed. The CPU takes the buses one half clock cycle after HLDA goes low. INTR (Input):  INTERRUPT REQUEST is used as a general purpose interrupt. It is sampled only during thenext to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued.  During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted. INTA (Output):  INTERRUPT ACKNOWLEDGE: is used instead of (and has the same timing as) RD during theInstruction cycle after an INTR is accepted.  It can be used to activate the 8259 Interrupt chip or some other interrupt port. RESTART INTERRUPTS: These three inputs have the same timing as INTR except they cause an internal RESTART to be automatically inserted.  RST 7.5 Highest Priority  RST 6.5  RST 5.5 Lowest Priority TRAP (Input):  Trap interrupt is a non maskable restart interrupt. It is recognized at the same time as INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt. RESET IN (Input):  Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flipflops.  None of the other flags or registers (except the instruction register) are affected The CPU is held in the reset condition as long as Reset is applied. RESET OUT (Output): Indicates CPlJ is being reset. Can be used as a system RESET. The signal is synchronized to the processor clock. X1, X2 (Input):  Crystal or R/C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating frequency. CLK (Output):  Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period. IO/M (Output):  IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and Halt modes. SID (Input):  Serial input data line The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed. SOD (output):  Serial output data line. The output SOD is set or reset as specified by the SIM instruction. Vcc: +5 volt supply. Vss: Ground Reference. 3) MEMORY ORGANIZATION Memory Interfacing The memory is made up of semiconductor material used to store the programs and data. Three types of memory is,  Process memory  Primary or main memory  Secondary memory Typical EPROM and Static RAM A typical semiconductor memory IC will have n address pins, m data pins (or output pins).  Having two power supply pins (one for connecting required supply voltage (V and the other for connecting ground).  The control signals needed for static RAM are chip select (chip enable), read control (output enable) and write control (write enable).  The control signals needed for read operation in EPROM are chip select (chip enable) and read control (output enable). Decoder It is used to select the memory chip of processor during the execution of a program. No of IC's used for decoder is,  2-4 decoder (74LS139)  3-8 decoder (74LS138) Block Diagram of 2-4 Decoder Truth Table for 2-4 Decoder Example for Memory Interfacing Consider a system in which the full memory space 64kb is utilized for EPROM memory. Interface the EPROM with 8085 processor.  The memory capacity is 64 Kbytes. i.e  2n = 64 x 1000 bytes where n = address lines.  So, n = 16.  In this system the entire 16 address lines of the processor are connected to address input pins of memory IC in order to address the internal locations of memory.  The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to ground).  Since the processor is connected to EPROM, the active low RD pin is connected to active low output enable pin of EPROM.  The range of address for EPROM is 0000H to FFFFH. Memory Interfacing 4) TIMING DIAGRAM Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in a graphical format. The execution time is represented in T-states.  Instruction Cycle The time required to execute an instruction is called instruction cycle.  Machine Cycle The time required to access the memory or input/output devices is called machine cycle.  T-State  The machine cycle and instruction cycle takes multiple clock periods.  A portion of an operation carried out in one system clock period is called as T-state. Machine cycles of 8085 The 8085 microprocessor has 5 (seven) basic machine cycles. They are 1. Opcode fetch cycle (4T) 2. Memory read cycle (3 T) 3. Memory write cycle (3 T) 4. I/O read cycle (3 T) 5. I/O write cycle (3 T) Clock Signal 1.Opcode fetch machine cycle of 8085 :  Each instruction of the processor has one byte opcode.  The opcodes are stored in memory. So, the processor executes the opcode fetch machine cycle to fetch the opcode from memory.  Hence, every instruction starts with opcode fetch machine cycle.  The time taken by the processor to execute the opcode fetch cycle is 4T.  In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining T-states are used for internal operations by the processor. 2.Memory Read Machine Cycle of 8085:  The memory read machine cycle is executed by the processor to read a data byte from memory.  The processor takes 3T states to execute this cycle. The instructions which have more than one byte word size will use the machine cycle after the opcode fetch machine cycle. Memory Read Machine Cycle 3.Memory Write Machine Cycle of 8085  The memory write machine cycle is executed by the processor to write a data byte in a memory location.  The processor takes, 3T states to execute this machine cycle. Memory Write Machine Cycle 4. I/O Read Cycle of 8085  The I/O Read cycle is executed by the processor to read a data byte from I/O port or from the peripheral, which is I/O, mapped in the system.  The processor takes 3T states to execute this machine cycle.  The IN instruction uses this machine cycle during the execution. I/O Read Cycle Timing diagram for STA 526AH  STA means Store Accumulator -The contents of the accumulator is stored in the specified address(526A).  The opcode of the STA instruction is said to be 32H. It is fetched from the memory 41FFH(see fig). - OF machine cycle  Then the lower order memory address is read(6A). - Memory Read Machine Cycle  Read the higher order memory address (52).- Memory Read Machine Cycle  The combination of both the addresses are considered and the content from accumulator is written in 526A. - Memory Write Machine Cycle  Assume the memory address for the instruction and let the content of accumulator is C7H. So, C7H from accumulator is now stored in 526A. Timing Diagram for STA 526A H Timing diagram for INR M  Fetching the Opcode 34H from the memory 4105H. (OF cycle)  Let the memory address (M) be 4250H. (MR cycle -To read Memory address and data)  Let the content of that memory is 12H.  Increment the memory content from 12H to 13H. (MW machine cycle) 5) INTERRUPTS:  Interrupt is signals send by an external device to the processor, to request the processor to perform a particular task or work.  Mainly in the microprocessor based system the interrupts are used for data transfer between the peripheral and the microprocessor.  The processor will check the interrupts always at the 2nd T-state of last machine cycle.  If there is any interrupt it accept the interrupt and send the INTA (active low) signal to the peripheral.  The vectored address of particular interrupt is stored in program counter.  The processor executes an interrupt service routine (ISR) addressed in program counter.  It returned to main program by RET instruction. Types of Interrupts: It supports two types of interrupts.  Hardware  Software Software interrupts:  The software interrupts are program instructions. These instructions are inserted at desired locations in a program.  The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for these interrupts can be calculated as follows.  Interrupt number 8 = vector address  For RST 5,5 8 = 40 = 28H Vector addresses of all interrupts. Hardware interru pts:  An external device initiates the hardware interrupts and placing an appropriate signal at the interrupt pin of the processor.  If the interrupt is accepted then the processor executes an interrupt service routine. The 8085 has five hardware interrupts (1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR (1)TRAP:  This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable.  TRAP bas the highest priority and vectored interrupt.  TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and remain high until it is acknowledged.  In sudden power failure, it executes a ISR and send the data from main memory to backup memory.  The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is recognized).  There are two ways to clear TRAP interrupt. 1.By resetting microprocessor (External signal) 2.By giving a high TRAP ACKNOWLEDGE (Internal signal) (2)RST 7.5:  The RST 7.5 interrupt is a maskable interrupt.  It has the second highest priority.  It is edge sensitive. ie. Input goes to high and no need to maintain high state until it recognized.  Maskable interrupt. It is disabled by, 1.DI instruction 2.System or processor reset. 3.After reorganization of interrupt.  Enabled by EI instruction. (3)RST 6.5 and 5.5:  The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay high until it recognized.  Maskable interrupt. It is disabled by, 1.DI, SIM instruction 2.System or processor reset. 3.After reorganization of interrupt.  Enabled by EI instruction.  The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.  INTR is a maskable interrupt. It is disabled by, 1.DI, SIM instruction 2.System or processor reset. 3.After reorganization of interrupt  Enabled by EI instruction.  Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the address of ISR.  It has lowest priority.  It is a level sensitive interrupts. ie. Input goes to high and it is necessary to maintain high state until it recognized. The following sequence of events occurs when INTR signal goes high. 1. The 8085 checks the status of INTR signal during execution of each instruction. 2. If INTR signal is high, then 8085 complete its current instruction and sends active low interrupt acknowledge signal, if the interrupt is enabled. 3. In response to the acknowledge signal, external logic places an instruction OPCODE on the data bus. In the case of multibyte instruction, additional interrupt acknowledge machine cycles are generated by the 8085 to transfer the additional bytes into the microprocessor. 4. On receiving the instruction, the 8085 save the address of next instruction on