Lecture notes on Microcontroller

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Microcontrollers 4 Sem ECE/TCE Microcontrollers Notes for IV Sem ECE/TCE Students Saneesh Cleatus Thundiyil Associate. Professor, Department of Electronics and Communication Engineering, BMS Institute of Technology Bangalore - 64 Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 1 Microcontrollers 4 Sem ECE/TCE SYLLABUS MICROCONTROLLERS (Common to EC/TC/EE/IT/BM/ML) Sub Code : 10ES42 IA Marks : 25 Hrs/ Week : 04 Exam Hours : 03 Total Hrs. : 52 Exam Marks : 100 UNIT 1: Microprocessors and microcontroller. Introduction, Microprocessors and Microcontrollers, RISC & CISC CPU Architectures, Harvard & Von- Neumann CPU architecture, Computer software. The 8051 Architecture: Introduction, Architecture of 8051, Pin diagram of 8051, Memory organization, External Memory interfacing, Stacks. 6 Hrs UNIT 2: Addressing Modes: Introduction, Instruction syntax, Data types, Subroutines, Addressing modes: Immediate addressing , Register addressing, Direct addressing, Indirect addressing, relative addressing, Absolute addressing, Long addressing, Indexed addressing, Bit inherent addressing, bit direct addressing. Instruction set: Instruction timings, 8051 instructions: Data transfer instructions, Arithmetic instructions, Logical instructions, Branch instructions, Subroutine instructions, Bit manipulation instruction. 6 Hrs UNIT 3: 8051 programming: Assembler directives, Assembly language programs and Time delay calculations. 6 Hrs UNIT 4: 8051 Interfacing and Applications: Basics of I/O concepts, I/O Port Operation, Interfacing 8051 to LCD, Keyboard, parallel and serial ADC, DAC, Stepper motor interfacing and DC motor interfacing and programming 7 Hrs UNIT 5: 8051 Interrupts and Timers/counters: Basics of interrupts, 8051 interrupt structure, Timers and Counters, 8051 timers/counters, programming 8051 timers in assembly and C . 6 Hrs UNIT 6: 8051 Serial Communication: Data communication, Basics of Serial Data Communication, 8051 Serial Communication, connections to RS-232, Serial communication Programming in assembly and C. 8255A Programmable Peripheral Interface:, Architecture of 8255A, I/O addressing,, I/O devices interfacing with 8051 using 8255A. 6 Hrs Course Aim – The MSP430 microcontroller is ideally suited for development of low-power embedded systems that must run on batteries for many years. There are also applications where MSP430 microcontroller must operate on energy harvested from the environment. This is possible due to the ultra-low power operation of MSP430 and the fact that it provides a complete system solution including a RISC CPU, flash memory, on-chip data converters and on-chip peripherals. Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 2 Microcontrollers 4 Sem ECE/TCE UNIT 7: Motivation for MSP430microcontrollers – Low Power embedded systems, On-chip peripherals (analog and digital), low-power RF capabilities. Target applications (Single- chip, low cost, low power, high performance system design). 2 Hrs MSP430 RISC CPU architecture, Compiler-friendly features, Instruction set, Clock system, Memory subsystem. Key differentiating factors between different MSP430 families. 2 Hrs Introduction to Code Composer Studio (CCS v4). Understanding how to use CCS for Assembly, C, Assembly+C projects for MSP430 microcontrollers. Interrupt programming. 3 Hrs Digital I/O – I/O ports programming using C and assembly, Understanding the muxing scheme of the MSP430 pins. 2 Hrs UNIT 8: On-chip peripherals. Watchdog Timer, Comparator, Op-Amp, Basic Timer, Real Time Clock (RTC), ADC, DAC, SD16, LCD, DMA. 2 Hrs Using the Low-power features of MSP430. Clock system, low-power modes, Clock request feature, Low-power programming and Interrupt. 2 Hrs Interfacing LED, LCD, External memory. Seven segment LED modules interfacing. Example – Real-time clock. 2 Hrs Case Studies of applications of MSP430 - Data acquisition system, Wired Sensor network, Wireless sensor network with Chipcon RF interfaces. 3 Hrs TEXT BOOKS: 1. “The 8051 Microcontroller and Embedded Systems – using assembly and C ”-, Muhammad Ali Mazidi and Janice Gillespie Mazidi and Rollin D. McKinlay; PHI, 2006 / Pearson, 2006 2. “MSP430 Microcontroller Basics”, John Davies, Elsevier, 2010 (Indian edition available) REFERENCE BOOKS: 1. “The 8051 Microcontroller Architecture, Programming & Applications”, 2e Kenneth J. Ayala ;, Penram International, 1996 / Thomson Learning 2005. 2. “The 8051 Microcontroller”, V.Udayashankar and MalikarjunaSwamy, TMH, 2009 3. MSP430 Teaching CD-ROM, Texas Instruments, 2008 (can be requested http://www.uniti.in ) 4. Microcontrollers: Architecture, Programming, Interfacing and System Design”,Raj Kamal, “Pearson Education, 2005 Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 3 Microcontrollers 4 Sem ECE/TCE UNIT - 1 1.1 MICROPROCESSORS AND MICROCONTROLLERS Microprocessor Microcontroller Arithmetic and logic ALU Timer/ IO Ports unit Counter Accumulator Interrupt Accumulator Registers Circuits Internal Working Registers Internal RAM ROM Program Counter Stack Pointer Stack Pointer Clock Circuits Program Counter Clock Circuit Interrupt circuit Block diagram of microprocessor Block diagram of microcontroller Microprocessor contains ALU, General purpose Microcontroller contains the circuitry of registers, stack pointer, program counter, clock microprocessor, and in addition it has built in timing circuit, interrupt circuit ROM, RAM, I/O Devices, Timers/Counters etc. It has many instructions to move data between It has few instructions to move data between memory and CPU memory and CPU Few bit handling instruction It has many bit handling instructions Less number of pins are multifunctional More number of pins are multifunctional Single memory map for data and code Separate memory map for data and code (program) (program) Access time for memory and IO are more Less access time for built in memory and IO. Microprocessor based system requires It requires less additional hardwares additional hardware More flexible in the design point of view Less flexible since the additional circuits which is residing inside the microcontroller is fixed for a particular microcontroller Large number of instructions with flexible Limited number of instructions with few addressing modes addressing modes Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 4 Microcontrollers 4 Sem ECE/TCE 1.2. RISC AND CISC CPU ARCHITECTURES Microcontrollers with small instruction set are called reduced instruction set computer (RISC) machines and those with complex instruction set are called complex instruction set computer (CISC). Intel 8051 is an example of CISC machine whereas microchip PIC 18F87X is an example of RISC machine. RISC CISC Instruction takes one or two cycles Instruction takes multiple cycles Only load/store instructions are used to access In additions to load and store instructions, memory memory access is possible with other instructions also. Instructions executed by hardware Instructions executed by the micro program Fixed format instruction Variable format instructions Few addressing modes Many addressing modes Few instructions Complex instruction set Most of the have multiple register banks Single register bank Highly pipelined Less pipelined Complexity is in the compiler Complexity in the microprogram Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 5 Microcontrollers 4 Sem ECE/TCE 1.2. HARVARD & VON- NEUMANN CPU ARCHITECTURE Von-Neumann (Princeton architecture) Harvard architecture Data Data Program Data Memory Memory Address Bus CPU CPU Program Data Data Memory Memory Address Bus Address Bus Von-Neumann (Princeton architecture) Harvard architecture It uses single memory space for both It has separate program memory and data instructions and data. memory It is not possible to fetch instruction code and Instruction code and data can be fetched data simultaneously Execution of instruction takes more machine Execution of instruction takes less machine cycle cycle Uses CISC architecture Uses RISC architecture Instruction pre-fetching is a main feature Instruction parallelism is a main feature Also known as control flow or control driven Also known as data flow or data driven computers computers Simplifies the chip design because of single Chip design is complex due to separate memory memory space space Eg. 8085, 8086, MC6800 Eg. General purpose microcontrollers, special DSP chips etc. Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 6 Microcontrollers 4 Sem ECE/TCE 1.3 COMPUTER SOFTWARE A set of instructions written in a specific sequence for the computer to solve a specific task is called a program and software is a collection of such programs. The program stored in the computer memory in the form of binary numbers is called machine instructions. The machine language program is called object code. An assembly language is a mnemonic representation of machine language. Machine language and assembly language are low level languages and are processor specific. The assembly language program the programmer enters is called source code. The source code (assembly language) is translated to object code (machine language) using assembler. Programs can be written in high level languages such as C, C++ etc. High level language will be converted to machine language using compiler or interpreter. Compiler reads the entire program and translate into the object code and then it is executed by the processor. Interpreter takes one statement of the high level language as input and translate it into object code and then executes. 1.4 THE 8051 ARCHITECTURE Introduction Salient features of 8051 microcontroller are given below.  Eight bit CPU  On chip clock oscillator  4Kbytes of internal program memory (code memory) ROM  128 bytes of internal data memory RAM  64 Kbytes of external program memory address space.  64 Kbytes of external data memory address space.  32 bi directional I/O lines (can be used as four 8 bit ports or 32 individually addressable I/O lines)  Two 16 Bit Timer/Counter :T0, T1  Full Duplex serial data receiver/transmitter  Four Register banks with 8 registers in each bank.  Sixteen bit Program counter (PC) and a data pointer (DPTR)  8 Bit Program Status Word (PSW)  8 Bit Stack Pointer  Five vector interrupt structure (RESET not considered as an interrupt.)  8051 CPU consists of 8 bit ALU with associated registers like accumulator ‘A’ , B register, PSW, SP, 16 bit program counter, stack pointer.  ALU can perform arithmetic and logic functions on 8 bit variables.  8051 has 128 bytes of internal RAM which is divided into o Working registers 00 – 1F o Bit addressable memory area 20 – 2F o General purpose memory area (Scratch pad memory) 30-7F Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 7 Microcontrollers 4 Sem ECE/TCE The 8051 architecture. I/O A0-A7 ALU PSW Port 0 SFR D0-D7 General I/O Purpose A B RAM Port 1 I/O A8- Port 2 A15 ROM DPTR PC I/O DPH INT DPL CNTR Port 3 SERIAL RD/WR E IE A IP System General ALE Timing PCON purpose PSEN area SBUF XTAL1 System SCON interrupt TCON Bit addressible XTAL2 timers area TMOD RESET Register Bank 3 TL0 Data Register Bank 2 TH0 buffers Register Bank 1 TL1 Register Bank 0 TH1 Memory VCC control SFR and GND General Purpose RAM  8051 has 4 K Bytes of internal ROM. The address space is from 0000 to 0FFFh. If the program size is more than 4 K Bytes 8051 will fetch the code automatically from external memory.  Accumulator is an 8 bit register widely used for all arithmetic and logical operations. Accumulator is also used to transfer data between external memory. B register is used along with Accumulator for multiplication and division. A and B registers together is also called MATH registers. Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 8 Microcontrollers 4 Sem ECE/TCE  PSW (Program Status Word). This is an 8 bit register which contains the arithmetic status of ALU and the bank select bits of register banks. CY AC F0 RS1 RS0 OV - P CY - carry flag AC - auxiliary carry flag F0 - available to the user for general purpose RS1,RS0 - register bank select bits OV - overflow P - parity  Stack Pointer (SP) – it contains the address of the data item on the top of the stack. Stack may reside anywhere on the internal RAM. On reset, SP is initialized to 07 so that the default stack will start from address 08 onwards.  Data Pointer (DPTR) – DPH (Data pointer higher byte), DPL (Data pointer lower byte). This is a 16 bit register which is used to furnish address information for internal and external program memory and for external data memory.  Program Counter (PC) – 16 bit PC contains the address of next instruction to be executed. On reset PC will set to 0000. After fetching every instruction PC will increment by one. 1.5 PIN DIAGRAM Pinout Description Pins 1-8 PORT 1. Each of these pins can be configured as an input or an output. Pin 9 RESET. A logic one on this pin disables the microcontroller and clears the contents of most registers. In other words, the positive voltage on this pin resets the microcontroller. By applying logic zero to this pin, the program starts execution from the beginning. Pins10-17 PORT 3. Similar to port 1, each of these pins can serve as general input or output. Besides, all of them have alternative functions Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 9 Microcontrollers 4 Sem ECE/TCE Pin 10 RXD. Serial asynchronous communication input or Serial synchronous communication output. Pin 11 TXD. Serial asynchronous communication output or Serial synchronous communication clock output. Pin 12 INT0.External Interrupt 0 input Pin 13 INT1. External Interrupt 1 input Pin 14 T0. Counter 0 clock input Pin 15 T1. Counter 1 clock input Pin 16 WR. Write to external (additional) RAM Pin 17 RD. Read from external RAM Pin 18, 19 XTAL2, XTAL1. Internal oscillator input and output. A quartz crystal which specifies operating frequency is usually connected to these pins. Pin 20 GND. Ground. Pin 21-28 Port 2. If there is no intention to use external memory then these port pins are configured as general inputs/outputs. In case external memory is used, the higher address byte, i.e. addresses A8-A15 will appear on this port. Even though memory with capacity of 64Kb is not used, which means that not all eight port bits are used for its addressing, the rest of them are not available as inputs/outputs. Pin 29 PSEN. If external ROM is used for storing program then a logic zero (0) appears on it every time the microcontroller reads a byte from memory. Pin 30 ALE. Prior to reading from external memory, the microcontroller puts the lower address byte (A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE pin, the external latch latches the state of P0 and uses it as a memory chip address. Immediately after that, the ALE pin is returned its previous logic state and P0 is now used as a Data Bus. Pin 31 EA. By applying logic zero to this pin, P2 and P3 are used for data and address transmission with no regard to whether there is internal memory or not. It means that even there is a program written to the microcontroller, it will not be executed. Instead, the program written to external ROM will be executed. By applying logic one to the EA pin, the microcontroller will use both memories, first internal then external (if exists). Pin 32-39 PORT 0. Similar to P2, if external memory is not used, these pins can be used as general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when the ALE pin is driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0). Pin 40 VCC. +5V power supply. Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 10 Microcontrollers 4 Sem ECE/TCE 1.6 MEMORY ORGANIZATION Internal RAM organization R7 1F R6 1E R5 1D 7F 78 7F R4 1C 2F R3 1B 77 70 7E 2E R2 1A 6F 68 . 2D R1 19 67 60 . R0 18 2C R7 17 5F 58 . 2B R6 16 57 50 . 2A R5 15 4F 48 . R4 14 29 R3 13 47 40 . 28 R2 12 . 3F 38 27 R1 11 . 37 30 R0 10 26 R7 0F 2F 28 25 32 R6 0E 27 20 24 R5 0D 31 1F 18 R4 0C 23 30 R3 0B 17 10 22 R2 0A 0F 08 21 R1 09 07 00 R0 08 20 General purpose memory R7 07 R6 06 R5 05 R4 04 Bit addressable memory R3 03 R2 02 R1 01 R0 00 Working Registers Register Banks: 00h to 1Fh. The 8051 uses 8 general-purpose registers R0 through R7 (R0, R1, R2, R3, R4, R5, R6, and R7). There are four such register banks. Selection of register bank can be done through RS1,RS0 bits of PSW. On reset, the default Register Bank 0 will be selected. Bit Addressable RAM: 20h to 2Fh . The 8051 supports a special feature which allows access to bit variables. This is where individual memory bits in Internal RAM can be set or cleared. In all there are 128 bits numbered 00h to 7Fh. Being bit variables any one variable can have a value 0 or 1. A bit variable can be set with a command such as SETB and cleared with a command such as CLR. Example instructions are: SETB 25h ; sets the bit 25h (becomes 1) CLR 25h ; clears bit 25h (becomes 0) Note, bit 25h is actually bit 5 of Internal RAM location 24h. The Bit Addressable area of the RAM is just 16 bytes of Internal RAM located between 20h and 2Fh. General Purpose RAM: 30h to 7Fh. Even if 80 bytes of Internal RAM memory are available for general-purpose data storage, user should take care while using the memory location from 00 -2Fh Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 11 BANK 0 BANK 1 BANK 2 BANK 3 Microcontrollers 4 Sem ECE/TCE since these locations are also the default register space, stack space, and bit addressable space. It is a good practice to use general purpose memory from 30 – 7Fh. The general purpose RAM can be accessed using direct or indirect addressing modes. 1.7 EXTERNAL MEMORY INTERFACING Eg. Interfacing of 16 K Byte of RAM and 32 K Byte of EPROM to 8051 Number of address lines required for 16 Kbyte memory is 14 lines and that of 32Kbytes of memory is 15 lines. The connections of external memory is shown below. PSEN PSEN A14 A14 A13 A13 A13 A12 A12 A12 … .. 32 Kbyte A9 . A8 A8 . RAM WE WR 16 Kbyte . OE RD A3 A7 RAM AL A2 LE .. E A1 A0-A7 A0-A7 8051 A1 A0 A0 __ LOWER BYTE EA ADDRESS GND AD0 – AD7 DAT DAT A A O/P O/P 8 8 AD0 - DATA BUS AD0 – AD7 AD7 The lower order address and data bus are multiplexed. De-multiplexing is done by the latch. Initially the address will appear in the bus and this latched at the output of latch using ALE signal. The output of the latch is directly connected to the lower byte address lines of the memory. Later data will be available in this bus. Still the latch output is address it self. The higher byte of address bus is directly connected to the memory. The number of lines connected depends on the memory size. The RD and WR (both active low) signals are connected to RAM for reading and writing the data. PSEN of microcontroller is connected to the output enable of the ROM to read the data from the memory. EA (active low) pin is always grounded if we use only external memory. Otherwise, once the program size exceeds internal memory the microcontroller will automatically switch to external memory. Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 12 Microcontrollers 4 Sem ECE/TCE 1.8 STACK A stack is a last in first out memory. In 8051 internal RAM space can be used as stack. The address of the stack is contained in a register called stack pointer. Instructions PUSH and POP are used for stack operations. When a data is to be placed on the stack, the stack pointer increments before storing the data on the stack so that the stack grows up as data is stored (pre-increment). As the data is retrieved from the stack the byte is read from the stack, and then SP decrements to point the next available byte of stored data (post decrement). The stack pointer is set to 07 when the 8051 resets. So that default stack memory starts from address location 08 onwards (to avoid overwriting the default register bank ie., bank 0). Eg; Show the stack and SP for the following. SP=07 //CONTENT OF SP IS 07 (DEFAULT VALUE) MOV R6, 25H R6=25H //CONTENT OF R6 IS 25H MOV R1, 12H R1=12H //CONTENT OF R1 IS 12H MOV R4, 0F3H R4=F3H //CONTENT OF R4 IS F3H PUSH 6 SP=08 08=06=25H //CONTENT OF 08 IS 25H PUSH 1 SP=09 09=01=12H //CONTENT OF 09 IS 12H PUSH 4 SP=0A 0A=04=F3H //CONTENT OF 0A IS F3H POP 6 06=0A=F3H SP=09 //CONTENT OF 06 IS F3H POP 1 01=09=12H SP=08 //CONTENT OF 01 IS 12H POP 4 04=08=25H SP=07 //CONTENT OF 04 IS 25H Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 13 Microcontrollers 4 Sem ECE/TCE UNIT 2 2.1 INSTRUCTION SYNTAX. General syntax for 8051 assembly language is as follows. LABEL: OPCODE OPERAND ;COMMENT LABEL : (THIS IS NOT NECESSARY UNLESS THAT SPECIFIC LINE HAS TO BE ADDRESSED). The label is a symbolic address for the instruction. When the program is assembled, the label will be given specific address in which that instruction is stored. Unless that specific line of instruction is needed by a branching instruction in the program, it is not necessary to label that line. OPCODE: Opcode is the symbolic representation of the operation. The assembler converts the opcode to a unique binary code (machine language). OPERAND: While opcode specifies what operation to perform, operand specifies where to perform that action. The operand field generally contains the source and destination of the data. In some cases only source or destination will be available instead of both. The operand will be either address of the data, or data itself. COMMENT: Always comment will begin with ; or // symbol. To improve the program quality, programmer may always use comments in the program. 2.2 ADDRESSING MODES Various methods of accessing the data are called addressing modes. 8051 addressing modes are classified as follows. 1. Immediate addressing. 2. Register addressing. 3. Direct addressing. 4. Indirect addressing. 5. Relative addressing. 6. Absolute addressing. 7. Long addressing. 8. Indexed addressing. 9. Bit inherent addressing. 10. Bit direct addressing. 1. Immediate addressing. In this addressing mode the data is provided as a part of instruction itself. In other words data immediately follows the instruction. Eg. MOV A,30H ADD A, 83 Symbol indicates the data is immediate. Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 14 Microcontrollers 4 Sem ECE/TCE 2. Register addressing. In this addressing mode the register will hold the data. One of the eight general registers (R0 to R7) can be used and specified as the operand. Eg. MOV A,R0 ADD A,R6 R0 – R7 will be selected from the current selection of register bank. The default register bank will be bank 0. 3. Direct addressing There are two ways to access the internal memory. Using direct address and indirect address. Using direct addressing mode we can not only address the internal memory but SFRs also. In direct addressing, an 8 bit internal data memory address is specified as part of the instruction and hence, it can specify the address only in the range of 00H to FFH. In this addressing mode, data is obtained directly from the memory. Eg. MOV A,60h ADD A,30h 4. Indirect addressing The indirect addressing mode uses a register to hold the actual address that will be used in data movement. Registers R0 and R1 and DPTR are the only registers that can be used as data pointers. Indirect addressing cannot be used to refer to SFR registers. Both R0 and R1 can hold 8 bit address and DPTR can hold 16 bit address. Eg. MOV A,R0 ADD A,R1 MOVX A,DPTR 5. Indexed addressing. In indexed addressing, either the program counter (PC), or the data pointer (DTPR)—is used to hold the base address, and the A is used to hold the offset address. Adding the value of the base address to the value of the offset address forms the effective address. Indexed addressing is used with JMP or MOVC instructions. Look up tables are easily implemented with the help of index addressing. Eg. MOVC A, A+DPTR // copies the contents of memory location pointed by the sum of the accumulator A and the DPTR into accumulator A. MOVC A, A+PC // copies the contents of memory location pointed by the sum of the accumulator A and the program counter into accumulator A. 6. Relative Addressing. Relative addressing is used only with conditional jump instructions. The relative address, (offset), is an 8 bit signed number, which is automatically added to the PC to make the address of the next instruction. The 8 bit signed offset value gives an address range of +127 to —128 locations. The jump destination is usually specified using a label and the assembler calculates the jump offset accordingly. The advantage of relative addressing is that the program code is easy to relocate and the address is relative to position in the memory. Eg. SJMP LOOP1 JC BACK 7. Absolute addressing Absolute addressing is used only by the AJMP (Absolute Jump) and ACALL (Absolute Call) instructions. These are 2 bytes instructions. The absolute addressing mode specifies the lowest 11 bit of the memory address as part of the instruction. The upper 5 bit of the destination address are Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 15 Microcontrollers 4 Sem ECE/TCE the upper 5 bit of the current program counter. Hence, absolute addressing allows branching only within the current 2 Kbyte page of the program memory. Eg. AJMP LOOP1 ACALL LOOP2 8. Long Addressing The long addressing mode is used with the instructions LJMP and LCALL. These are 3 byte instructions. The address specifies a full 16 bit destination address so that a jump or a call can be made to a location within a 64 Kbyte code memory space. Eg. LJMP FINISH LCALL DELAY 9. Bit Inherent Addressing In this addressing, the address of the flag which contains the operand, is implied in the opcode of the instruction. Eg. CLR C ; Clears the carry flag to 0 10. Bit Direct Addressing In this addressing mode the direct address of the bit is specified in the instruction. The RAM space 20H to 2FH and most of the special function registers are bit addressable. Bit address values are between 00H to 7FH. Eg. CLR 07h ; Clears the bit 7 of 20h RAM space SETB 07H ; Sets the bit 7 of 20H RAM space. 2.3 INSTRUCTION SET. 1. Instruction Timings The 8051 internal operations and external read/write operations are controlled by the oscillator clock. T-state, Machine cycle and Instruction cycle are terms used in instruction timings. T-state is defined as one subdivision of the operation performed in one clock period. The terms 'T- state' and 'clock period' are often used synonymously. Machine cycle is defined as 12 oscillator periods. A machine cycle consists of six states and each state lasts for two oscillator periods. An instruction takes one to four machine cycles to execute an instruction. Instruction cycle is defined as the time required for completing the execution of an instruction. The 8051 instruction cycle consists of one to four machine cycles. Eg. If 8051 microcontroller is operated with 12 MHz oscillator, find the execution time for the following four instructions. 1. ADD A, 45H 2. SUBB A, 55H 3. MOV DPTR, 2000H 4. MUL AB Since the oscillator frequency is 12 MHz, the clock period is, Clock period = 1/12 MHz = 0.08333 µS. Time for 1 machine cycle = 0.08333 µS x 12 =1 µS. Instruction No. of machine cycles Execution time 1. ADD A, 45H 1 1 µs Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 16 Microcontrollers 4 Sem ECE/TCE 2. SUBB A, 55H 2 2 µs 3. MOV DPTR, 2000H 2 2 µs 4. MUL AB 4 4 µs 2. 8051 Instructions The instructions of 8051 can be broadly classified under the following headings. 1. Data transfer instructions 2. Arithmetic instructions 3. Logical instructions 4. Branch instructions 5. Subroutine instructions 6. Bit manipulation instructions Data transfer instructions. In this group, the instructions perform data transfer operations of the following types. a. Move the contents of a register Rn to A i. MOV A,R2 ii. MOV A,R7 b. Move the contents of a register A to Rn i. MOV R4,A ii. MOV R1,A c. Move an immediate 8 bit data to register A or to Rn or to a memory location(direct or indirect) i. MOV A, 45H iv. MOV R0, 0E8H ii. MOV R6, 51H v. MOV DPTR, 0F5A2H iii. MOV 30H, 44H vi. MOV DPTR, 5467H d. Move the contents of a memory location to A or A to a memory location using direct and indirect addressing i. MOV A, 65H iii. MOV 45H, A ii. MOV A, R0 iv. MOV R1, A e. Move the contents of a memory location to Rn or Rn to a memory location using direct addressing i. MOV R3, 65H ii. MOV 45H, R2 f. Move the contents of memory location to another memory location using direct and indirect addressing i. MOV 47H, 65H ii. MOV 45H, R0 g. Move the contents of an external memory to A or A to an external memory i. MOVX A,R1 iii. MOVX A,DPTR ii. MOVX R0,A iv. MOVXDPTR,A h. Move the contents of program memory to A i. MOVC A, A+PC ii. MOVC A, A+DPTR Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 17 Microcontrollers 4 Sem ECE/TCE FIG. Addressing Using MOV, MOVX and MOVC i. Push and Pop instructions SP=07 //CONTENT OF SP IS 07 (DEFAULT VALUE) MOV R6, 25H R6=25H //CONTENT OF R6 IS 25H MOV R1, 12H R1=12H //CONTENT OF R1 IS 12H MOV R4, 0F3H R4=F3H //CONTENT OF R4 IS F3H PUSH 6 SP=08 08=06=25H //CONTENT OF 08 IS 25H PUSH 1 SP=09 09=01=12H //CONTENT OF 09 IS 12H PUSH 4 SP=0A 0A=04=F3H //CONTENT OF 0A IS F3H POP 6 06=0A=F3H SP=09 //CONTENT OF 06 IS F3H POP 1 01=09=12H SP=08 //CONTENT OF 01 IS 12H POP 4 04=08=25H SP=07 //CONTENT OF 04 IS 25H j. Exchange instructions The content of source ie., register, direct memory or indirect memory will be exchanged with the contents of destination ie., accumulator. i. XCH A,R3 ii. XCH A,R1 iii. XCH A,54h k. Exchange digit. Exchange the lower order nibble of Accumulator (A0-A3) with lower order nibble of the internal RAM location which is indirectly addressed by the register. i. XCHD A,R1 ii. XCHD A,R0 Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 18 Microcontrollers 4 Sem ECE/TCE Arithmetic instructions. The 8051 can perform addition, subtraction. Multiplication and division operations on 8 bit numbers. Addition In this group, we have instructions to i. Add the contents of A with immediate data with or without carry. i. ADD A, 45H ii. ADDC A, OB4H ii. Add the contents of A with register Rn with or without carry. i. ADD A, R5 ii. ADDC A, R2 iii. Add the contents of A with contents of memory with or without carry using direct and indirect addressing i. ADD A, 51H ii. ADDC A, 75H iii. ADD A, R1 iv. ADDC A, R0 CY AC and OV flags will be affected by this operation. Subtraction In this group, we have instructions to i. Subtract the contents of A with immediate data with or without carry. i. SUBB A, 45H ii. SUBB A, OB4H ii. Subtract the contents of A with register Rn with or without carry. i. SUBB A, R5 ii. SUBB A, R2 iii. Subtract the contents of A with contents of memory with or without carry using direct and indirect addressing i. SUBB A, 51H ii. SUBB A, 75H iii. SUBB A, R1 iv. SUBB A, R0 CY AC and OV flags will be affected by this operation. Multiplication MUL AB. This instruction multiplies two 8 bit unsigned numbers which are stored in A and B register. After multiplication the lower byte of the result will be stored in accumulator and higher byte of result will be stored in B register. Eg. MOV A,45H ;A=45H MOV B,0F5H ;B=F5H MUL AB ;A x B = 45 x F5 = 4209 ;A=09H, B=42H Division Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 19 Microcontrollers 4 Sem ECE/TCE DIV AB. This instruction divides the 8 bit unsigned number which is stored in A by the 8 bit unsigned number which is stored in B register. After division the result will be stored in accumulator and remainder will be stored in B register. Eg. MOV A,45H ;A=0E8H MOV B,0F5H ;B=1BH DIV AB ;A / B = E8 /1B = 08 H with remainder 10H ;A = 08H, B=10H DA A (Decimal Adjust After Addition). When two BCD numbers are added, the answer is a non-BCD number. To get the result in BCD, we use DA A instruction after the addition. DA A works as follows.  If lower nibble is greater than 9 or auxiliary carry is 1, 6 is added to lower nibble.  If upper nibble is greater than 9 or carry is 1, 6 is added to upper nibble. Eg 1: MOV A,23H MOV R1,55H ADD A,R1 // A=78 DA A // A=78 no changes in the accumulator after da a Eg 2: MOV A,53H MOV R1,58H ADD A,R1 // A=ABh DA A // A=11, C=1 . ANSWER IS 111. Accumulator data is changed after DA A Increment: increments the operand by one. INC A INC Rn INC DIRECT INC Ri INC DPTR INC increments the value of source by 1. If the initial value of register is FFh, incrementing the value will cause it to reset to 0. The Carry Flag is not set when the value "rolls over" from 255 to 0. In the case of "INC DPTR", the value two-byte unsigned integer value of DPTR is incremented. If the initial value of DPTR is FFFFh, incrementing the value will cause it to reset to 0. Decrement: decrements the operand by one. DEC A DEC Rn DEC DIRECT DEC Ri DEC decrements the value of source by 1. If the initial value of is 0, decrementing the value will cause it to reset to FFh. The Carry Flag is not set when the value "rolls over" from 0 to FFh. Logical Instructions Logical AND ANL destination, source: ANL does a bitwise "AND" operation between source and destination, leaving the resulting value in destination. The value in source is not affected. "AND" instruction logically AND the bits of source and destination. ANL A,DATA ANL A, Rn ANL A,DIRECT ANL A,Ri ANL DIRECT,A ANL DIRECT, DATA Logical OR ORL destination, source: ORL does a bitwise "OR" operation between source and destination, Saneesh Cleatus Thundiyil BMS Institute of Technology, Bangalore – 64 20