Microprogrammed control ppt

microprogrammed control ppt morris mano and microprogramming in computer architecture ppt
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Dr.ShaneMatts,United States,Teacher
Published Date:23-07-2017
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1 Microprogramming Arvind Computer Science & Artificial Intelligence Lab M.I.T. Based on the material prepared by Arvind and Krste Asanovic 6.823 L4- 2 Arvind ISA to Microarchitecture Mapping • An ISA often designed for a particular microarchitectural style, e.g., –CISC ⇒ microcoded –RISC ⇒ hardwired, pipelined –VLIW ⇒ fixed latency in-order pipelines –JVM ⇒ software interpretation • But an ISA can be implemented in any microarchitectural style – Pentium-4: hardwired pipelined CISC (x86) machine (with some microcode support) – This lecture: a microcoded RISC (MIPS) machine – Intel will probably eventually have a dynamically scheduled out-of-order VLIW (IA-64) processor – PicoJava: A hardware JVM processor September 21, 2005 6.823 L4- 3 Arvind Microarchitecture: Implementation of an ISA control Controller status points lines Data path Structure: How components are connected. Static Behavior: How data moves between components Dynamic September 21, 2005 6.823 L4- 4 Arvind Microcontrol Unit Maurice Wilkes, 1954 Embed the control logic state table in a memory array op conditional code flip-flop Next state µ address Matrix A Matrix B Decoder Control lines to ALU, MUXs, Registers September 21, 2005 6.823 L4- 5 Arvind Microcoded Microarchitecture holds fixed busy? µcontroller microcode instructions zero? (ROM) opcode Datapath Data Addr Memory enMem holds user program (RAM) MemWrt written in macrocode instructions (e.g., MIPS, x86, etc.) September 21, 2005 6.823 L4- 6 Arvind The MIPS32 ISA • Processor State 32 32-bit GPRs, R0 always contains a 0 16 double-precision/32 single-precision FPRs FP status register, used for FP compares & exceptions PC, the program counter See H&P p129­ some other special registers 137 & Appendix C (online) for full • Data types description 8-bit byte, 16-bit half word 32-bit word for integers 32-bit word for single precision floating point 64-bit word for double precision floating point • Load/Store style instruction set data addressing modes- immediate & indexed branch addressing modes- PC relative & register indirect Byte addressable memory- big-endian mode All instructions are 32 bits September 21, 2005 6.823 L4- 7 Arvind MIPS Instruction Formats 6 5 5 5 5 6 0 rs rt rd 0 func rd ← (rs) func (rt) ALU opcode rs rt immediate rt ← (rs) op immediate ALUi 6 5 5 16 opcode rs rt displacement M(rs) + displacement Mem 6 5 5 16 opcode rs offset BEQZ, BNEZ 6 5 5 16 opcode rs JR, JALR 6 26 opcode offset J, JAL September 21, 2005 6.823 L4- 8 Arvind A Bus-based Datapath for MIPS Opcode zero? Busy? ldIR 32(PC) ldMA ldA ldB OpSel 31(Link) rd rt 2 rs RegSel MA 3 rd rt addr addr IR A B rs 32 GPRs ExtSel + PC ... Memory MemWrt Imm ALU RegWrt 2 Ext control ALU 32-bit Reg enReg enMem enImm enALU data data Bus 32 Microinstruction: register to register transfer (17 control signals) MA ← PC means RegSel = PC; enReg=yes; ldMA= yes B ← Regrt means RegSel = rt; enReg=yes; ldB = yes September 21, 2005 6.823 L4- 9 Arvind Memory Module addr busy Write(1)/Read(0) RAM we Enable din dout bus Assumption: Memory operates asynchronously and is slow as compared to Reg-to-Reg transfers September 21, 2005 6.823 L4- 10 Arvind Instruction Execution Execution of a MIPS instruction involves 1. instruction fetch 2. decode and register fetch 3. ALU operation 4. memory operation (optional) 5. write back to register file (optional) + the computation of the next instruction address September 21, 2005 6.823 L4- 11 Arvind Microprogram Fragments instr fetch: MA ← PC can be A ← PC treated as IR ← Memory PC ← A + 4 a macro dispatch on OPcode ALU: A ← Regrs B ← Regrt Regrd ← func(A,B) do instruction fetch ALUi: A ← Regrs B ← Imm sign extension ... Regrt ← Opcode(A,B) do instruction fetch September 21, 2005 6.823 L4- 12 Arvind Microprogram Fragments (cont.) LW: A ← Regrs B ← Imm MA ← A + B Regrt ← Memory do instruction fetch JumpTarg(A,B) = J: A ← PC A31:28,B25:0,00 B ← IR PC ← JumpTarg(A,B) do instruction fetch beqz: A ← Regrs If zero?(A) then go to bz-taken do instruction fetch bz-taken: A ← PC B ← Imm 2 PC ← A + B do instruction fetch September 21, 2005 6.823 L4- 13 Arvind MIPS Microcontroller: first attempt Opcode 6 zero? Busy (memory) latching the inputs µPC (state) may cause a How big s one-cycle delay is “s”? addr s ROM size ? µProgram ROM (opcode+status+s) = 2 words Word size ? data next = control+s bits state Control Signals (17) September 21, 2005 6.823 L4- 14 Arvind Microprogram in the ROM worksheet State Op zero? busy Control points next-state fetch MA ← PC fetch 0 1 fetch yes .... fetch 1 1 fetch no IR ← Memory fetch 1 2 fetch A ← PC fetch 2 3 fetch PC ← A + 4 ? 3 fetchALU PC ← A + 4 ALU 3 0 ALU A ← Regrs ALU 0 1 ALU B ← Regrt ALU 1 2 ALU Regrd ← func(A,B) fetch 2 0 September 21, 2005 6.823 L4- 15 Arvind Microprogram in the ROM State Op zero? busy Control points next-state fetch MA ← PC fetch 0 1 fetch yes .... fetch 1 1 fetch no IR ← Memory fetch 1 2 fetch A ← PC fetch 2 3 fetchALU PC ← A + 4 ALU 3 0 fetchALUi PC ← A + 4 ALUi 3 0 fetchLW PC ← A + 4 LW 3 0 fetchSW PC ← A + 4 SW 3 0 fetch J PC ← A + 4 J 3 0 fetchJAL PC ← A + 4 JAL 3 0 fetchJR PC ← A + 4 JR 3 0 fetchJALR PC ← A + 4 JALR 3 0 fetchbeqz PC ← A + 4 beqz 3 0 ... ALU A ← Regrs ALU 0 1 ALU B ← Regrt ALU 1 2 ALU Regrd ← func(A,B) fetch 2 0 September 21, 2005 6.823 L4- 16 Arvind Microprogram in the ROM Cont. State Op zero? busy Control points next-state ALUi A ← Regrs ALUi 0 1 ALUisExt B ← sExt (Imm) ALUi 1 16 2 ALUiuExt B ← uExt (Imm) ALUi 1 16 2 ALUi Regrd← Op(A,B) fetch 2 0 ... J A ← PC J 0 1 J B ← IR J 1 2 J PC ← JumpTarg(A,B) fetch 2 0 ... beqz A ← Regrs beqz 0 1 beqz yes A ← PC beqz 1 2 beqz no .... fetch 1 0 beqz B ← sExt (Imm) beqz 2 16 3 beqz PC ← A+B fetch 3 0 ... JumpTarg(A,B) = A31:28,B25:0,00 September 21, 2005 6.823 L4- 17 Arvind Size of Control Store / status & opcode w µPC / s addr (w+s) size = 2 x (c + s) next µPC Control ROM data Control signals / c MIPS: w = 6+2 c = 17 s = ? no. of steps per opcode = 4 to 6 + fetch-sequence no. of states ≈ (4 steps per op-group ) x op-groups + common sequences = 4 x 8 + 10 states = 42 states ⇒ s = 6 (8+6) Control ROM = 2 x 23 bits ≈ 48 Kbytes September 21, 2005 6.823 L4- 18 Arvind Reducing Control Store Size Control store has to be fast ⇒ expensive • Reduce the ROM height (= address bits) – reduce inputs by extra external logic each input bit doubles the size of the control store – reduce states by grouping opcodes find common sequences of actions – condense input status bits combine all exceptions into one, i.e., exception/no-exception • Reduce the ROM width – restrict the next-state encoding Next, Dispatch on opcode, Wait for memory, ... – encode control signals (vertical microcode) September 21, 2005 6.823 L4- 19 Arvind MIPS Controller V2 absolute (start of a predetermined sequence) ext Opcode op-group µPC µPC+1 +1 input encoding µPC (state) µPCSrc reduces ROM height zero jump address busy logic µJumpType = Control ROM next spin data fetch dispatch feqz fnez next-state encoding Control Signals (17) reduces ROM width September 21, 2005 6.823 L4- 20 Arvind Jump Logic µPCSrc = Case µJumpTypes next ⇒µPC+1 spin ⇒ if (busy) then µPC else µPC+1 fetch ⇒ absolute dispatch ⇒ op-group feqz ⇒ if (zero) then absolute else µPC+1 fnez ⇒ if (zero) then µPC+1 else absolute September 21, 2005