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High Speed Router Design

High Speed Router Design 8
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Dr.NeerajMittal,India,Teacher
Published Date:19-07-2017
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High Speed Router Design Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 1Overview  Introduction  Evolution of High-Speed Routers  High Speed Router Components: Lookup Algorithm Classification Switching Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 2What do switches/routers look like? Access routers e.g. ISDN, ADSL Core router Core ATM switch e.g. OC48c POS Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 3Dimensions, Power Consumption Cisco GSR 12416 Juniper M160 19” 19” Capacity: 160Gb/s Capacity: 80Gb/s Power: 4.2kW Power: 2.6kW 6ft 3ft 2ft 2.5ft Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 4Where high performance packet switches are used - Carrier Class Core Router - ATM Switch - Frame Relay Switch The Internet Core Edge Router Enterprise WAN access & Enterprise Campus Switch Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 5Where are routers? Ans: Points of Presence (POPs) POP3 POP2 POP1 D POP4 A B E POP5 POP6 C POP7 POP8 F Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 6Why the Need for Big/Fast/Large Routers? POP with large routers POP with smaller routers  Interfaces: Price 200k, Power 400W  Space, power, interface cost economics  About 50-60% of i/fs are used for interconnection within the POP.  Industry trend is towards large, single router per POP. Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 7Job of router architect  For a given set of features: Maximize capacity, C s.. t Power, P 5kW 3 Volume, V 2m Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 8Performance metrics 1. Capacity 3  “maximize C, s.t. volume 2m and power 5kW” 2. Throughput  Maximize usage of expensive long-haul links.  Trivial with work-conserving output-queued routers 3. Controllable Delay  Some users would like predictable delay.  This is feasible with output-queueing plus weighted fair queuing (WFQ). ( , ) ( , ) WFQ Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 9The Problem  Output queued switches are impractical Can’t I just use N separate R memory devices per output? R R output R 1 R DRAM R R R N NR NR Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 10 dataMemory Bandwidth Commercial DRAM  Memory speed is not keeping up with Moore’s Law. 1980 1983 1986 1989 1992 1995 1998 2001 1000 100 DRAM 1.1x / 18months 10 1 Moore’s Law 2x / 18 months 0.1 Router 0.01 Line Capacity Capacity 2x / 7 months 2.2x / 18months 0.001 Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 0.0001 11 Access Time (ns)Packet processing is getting harder CPU Instructions per minimum length packet since 1996 1000 100 10 1 1996 1997 1998 1999 2000 2001 Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 12Basic Ideas Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 13Forwarding Functions: ATM Switch  Lookup cell VCI/VPI in VC table.  Replace old VCI/VPI with new.  Forward cell to outgoing interface.  Transmit cell onto link. Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 14Functions: Ethernet (L2) Switch  Lookup frame destination address (DA) in forwarding table. If known, forward to correct port. If unknown, broadcast to all ports.  Learn source address (SA) of incoming frame.  Forward frame to outgoing interface.  Transmit frame onto link. Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 15Functions: IP Router  Lookup packet DA in forwarding table. If known, forward to correct port. If unknown, drop packet.  Decrement TTL, update header Cksum.  Forward packet to outgoing interface.  Transmit packet onto link. Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 16Basic Architectural Components Congestion Control Admission Control Reservation Control Routing Datapath: Output per-packet Policing Switching Scheduling processing Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 17Basic Architectural Components 3. 1. Output 2. Scheduling Forwarding Table Interconnect Forwarding Decision Forwarding Table Forwarding Decision Forwarding Table Forwarding Decision Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 18Generic Router Architecture Header Processing Data Hdr Data Hdr Queue Lookup Update Packet IP Address Header IP Address Next Hop 1M prefixes Address Buffer 1M packets Off-chip DRAM Off-chip DRAM Table Memory Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 19Generic Router Architecture Header Processing Buffer Lookup Update Manager IP Address Header Buffer Address Memory Table Header Processing Buffer Lookup Update Manager IP Address Header Buffer Address Memory Table Header Processing Buffer Lookup Update Manager IP Address Header Buffer Address Memory Table Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 20