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Vector Computers

Vector Computers
Joel Emer November 30, 2005 6.823, L221 Vector Computers Joel Emer Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology Based on the material prepared by Krste Asanovic and Arvind Joel Emer November 30, 2005 6.823, L222 Supercomputers Definition of a supercomputer: • Fastest machine in world at given task • A device to turn a computebound problem into an I/O bound problem • Any machine costing 30M+ • Any machine designed by Seymour Cray CDC6600 (Cray, 1964) regarded as first supercomputer Joel Emer November 30, 2005 6.823, L223 Supercomputer Applications Typical application areas • Military research (nuclear weapons, cryptography) • Scientific research • Weather forecasting • Oil exploration • Industrial design (car crash simulation) • Bioinformatics • Cryptography All involve huge computations on large data sets In 70s80s, Supercomputer ≡ Vector Machine Joel Emer November 30, 2005 6.823, L224 Loop Unrolled Code Schedule Int1 Int 2 M1 M2 FP+ FPx loop: ld f1, 0(r1) ld f2, 8(r1) loop: ld f1 ld f3, 16(r1) ld f4, 24(r1) ld f2 add r1, 32 ld f3 fadd f5 fadd f5, f0, f1 add r1 ld f4 fadd f6, f0, f2 fadd f6 Schedule fadd f7, f0, f3 fadd f7 fadd f8, f0, f4 fadd f8 sd f5, 0(r2) sd f5 sd f6, 8(r2) sd f6 sd f7, 16(r2) sd f7 sd f8, 24(r2) add r2 bne sd f8 add r2, 32 bne r1, r3, loop Joel Emer November 30, 2005 6.823, L225 Vector Supercomputers Epitomized by Cray1, 1976: • Scalar Unit – Load/Store Architecture • Vector Extension – Vector Registers –Vector Instructions • Implementation –Hardwired Control – Highly Pipelined Functional Units – Interleaved Memory System –No Data Caches –No Virtual Memory Joel Emer November 30, 2005 6.823, L226 Cray1 (1976) Core unit of the Cray 1 computer Image removed due to copyright restrictions. To view image, visit http://www.cray cyber.org/memory/scray.php. Joel Emer November 30, 2005 6.823, L227 Cray1 (1976) V0 V i V. Mask V1 V2 V j 64 Element V3 V. Length V4 V k Vector Registers V5 Single Port V6 V7 Memory FP Add S0 S FP Mul j S1 ( (A ) + j k m ) 16 banks of h S2 S FP Recip k S3 64bit words S i S4 (A ) 64 S 0 i Int Add + S5 T jk T Regs S6 Int Logic 8bit SECDED S7 Int Shift A0 80MW/sec data A1 ( (A ) + j k m ) Pop Cnt h A2 load/store A j A3 A i A4 (A ) A Addr Add 64 0 k A5 B jk A B Regs i A6 Addr Mul 320MW/sec A7 instruction buffer refill NIP CIP 64bitx16 LIP 4 Instruction Buffers memory bank cycle 50 ns processor cycle 12.5 ns (80MHz) Joel Emer November 30, 2005 6.823, L228 Vector Programming Model Scalar Registers Vector Registers r15 v15 r0 v0 0 1 2 VLRMAX1 Vector Length Register VLR v1 Vector Arithmetic v2 Instructions + + + + + + ADDV v3, v1, v2 v3 0 1 VLR1 Vector Load and Vector Register v1 Store Instructions LV v1, r1, r2 Memory Base, r1 Stride, r2 Joel Emer November 30, 2005 6.823, L229 Vector Code Example Scalar Code Vector Code C code LI R4, 64 LI VLR, 64 for (i=0; i64; i++) loop: LV V1, R1 Ci = Ai + Bi; L.D F0, 0(R1) LV V2, R2 L.D F2, 0(R2) ADDV.D V3, V1, V2 ADD.D F4, F2, F0 SV V3, R3 S.D F4, 0(R3) DADDIU R1, 8 DADDIU R2, 8 DADDIU R3, 8 DSUBIU R4, 1 BNEZ R4, loop Joel Emer November 30, 2005 6.823, L2210 Vector Instruction Set Advantages • Compact – one short instruction encodes N operations • Expressive, tells hardware that these N operations: – are independent – use the same functional unit – access disjoint registers – access registers in same pattern as previous instructions – access a contiguous block of memory (unitstride load/store) – access memory in a known pattern (strided load/store) • Scalable – can run same code on more parallel pipelines (lanes) Joel Emer November 30, 2005 6.823, L2211 Vector Arithmetic Execution • Use deep pipeline (= fast clock) to execute element V V V operations 1 2 3 • Simplifies control of deep pipeline because elements in vector are independent (= no hazards) Six stage multiply pipeline V3 v1 v2 Joel Emer November 30, 2005 6.823, L2212 Vector Instruction Execution ADDV C,A,B Execution using one Execution using pipelined functional four pipelined unit functional units A6 B6 A24 B24 A25 B25 A26 B26 A27 B27 A5 B5 A20 B20 A21 B21 A22 B22 A23 B23 A4 B4 A16 B16 A17 B17 A18 B18 A19 B19 A3 B3 A12 B12 A13 B13 A14 B14 A15 B15 C2 C8 C9 C10 C11 C1 C4 C5 C6 C7 C0 C0 C1 C2 C3 Joel Emer November 30, 2005 6.823, L2213 Vector Memory System Cray1, 16 banks, 4 cycle bank busy time, 12 cycle latency • Bank busy time: Cycles between accesses to same bank Base Stride Vector Registers Address Generator + 0 1 2 3 4 5 6 7 8 9 A B C D E F Memory Banks Joel Emer November 30, 2005 6.823, L2214 Vector Unit Structure Functional Unit Vector Registers Elements Elements Elements Elements 0, 4, 8, … 1, 5, 9, … 2, 6, 10, … 3, 7, 11, … Lane Memory Subsystem Joel Emer November 30, 2005 6.823, L2215 T0 Vector Microprocessor (1995) Lane Vector register elements striped over lanes 2425262728 29 3031 1617181920 21 2223 8 9 101112 13 1415 0 1 2 3 4 5 6 7 For more information, visit http://www.icsi.berkeley.edu/real/spert/t0intro.html Joel Emer November 30, 2005 6.823, L2216 Vector Instruction Parallelism Can overlap execution of multiple vector instructions – example machine has 32 elements per vector register and 8 lanes Load Unit Multiply Unit Add Unit load mul add time load mul add Instruction issue Complete 24 operations/cycle while issuing 1 short instruction/cycle Joel Emer November 30, 2005 Vector Chaining 6.823, L2217 • Vector version of register bypassing – introduced with Cray1 V V V V V LV v1 1 2 3 4 5 MULV v3,v1,v2 ADDV v5, v3, v4 Chain Chain Load Unit Mult. Add Memory Joel Emer November 30, 2005 6.823, L2218 Vector Chaining Advantage • Without chaining, must wait for last element of result to be written before starting dependent instruction Load Mul Time Add • With chaining, can start dependent instruction as soon as first result appears Load Mul Add Joel Emer November 30, 2005 6.823, L2219 Vector Startup Two components of vector startup penalty – functional unit latency (time through pipeline) – dead time or recovery time (time before another vector instruction can start down pipeline) Functional Unit Latency R X X X W First Vector Instruction R X X X W R X X X W R X X X W R X X X W Dead Time R X X X W R X X X W R X X X W Dead Time Second Vector Instruction R X X X W R X X X W Joel Emer November 30, 2005 6.823, L2220 Dead Time and Short Vectors No dead time 4 cycles dead time T0, Eight lanes No dead time 100 efficiency with 8 element vectors 64 cycles active Cray C90, Two lanes 4 cycle dead time Maximum efficiency 94 with 128 element vectors Joel Emer November 30, 2005 6.823, L2221 Vector MemoryMemory versus Vector Register Machines • Vector memorymemory instructions hold all vector operands in main memory • The first vector machines, CDC Star100 (‘73) and TI ASC (‘71), were memorymemory machines • Cray1 (’76) was first vector register machine Vector MemoryMemory Code Example Source Code ADDV C, A, B SUBV D, A, B for (i=0; iN; i++) Vector Register Code Ci = Ai + Bi; Di = Ai Bi; LV V1, A LV V2, B ADDV V3, V1, V2 SV V3, C SUBV V4, V1, V2 SV V4, D Joel Emer November 30, 2005 6.823, L2222 Vector MemoryMemory vs. Vector Register Machines • Vector memorymemory architectures (VMMA) require greater main memory bandwidth, why – All operands must be read in and out of memory • VMMAs make if difficult to overlap execution of multiple vector operations, why – M ust check dependencies on memory addresses • VMMAs incur greater startup latency – Scalar code was faster on CDC Star100 for vectors 100 elements – For Cray1, vector/scalar breakeven point was around 2 elements ⇒ Apart from CDC followons (Cyber205, ETA10) all major vector machines since Cray1 have had vector register architectures (we ignore vector memorymemory from now on) Joel Emer November 30, 2005 6.823, L2223 Automatic Code Vectorization for (i=0; i N; i++) Ci = Ai + Bi; Vectorized Code Scalar Sequential Code load load load load Iter. 1 load load add add add store store store load Iter Iter Vector Instruction . 1 . 2 load Iter. 2 Vectorization is a massive compiletime add reordering of operation sequencing ⇒ requires extensive loop dependence analysis store Time Joel Emer November 30, 2005 6.823, L2224 Vector Stripmining Problem: Vector registers have finite length Solution: Break loops into pieces that fit in registers, “Stripmining” ANDI R1, N, 63 N mod 64 MTC1 VLR, R1 Do remainder for (i=0; iN; i++) loop: Ci = Ai+Bi; LV V1, RA AB C DSLL R2, R1, 3 Multiply by 8 Remainder + DADDU RA, RA, R2 Bump pointer LV V2, RB DADDU RB, RB, R2 64 elements + ADDV.D V3, V1, V2 SV V3, RC DADDU RC, RC, R2 DSUBU N, N, R1 Subtract elements + LI R1, 64 MTC1 VLR, R1 Reset full length BGTZ N, loop Any more to do Joel Emer November 30, 2005 6.823, L2225 Vector Scatter/Gather Want to vectorize loops with indirect accesses: for (i=0; iN; i++) Ai = Bi + CDi Indexed load instruction (Gather) LV vD, rD Load indices in D vector LVI vC, rC, vD Load indirect from rC base LV vB, rB Load B vector ADDV.D vA, vB, vC Do add SV vA, rA Store result Joel Emer November 30, 2005 6.823, L2226 Vector Scatter/Gather Scatter example: for (i=0; iN; i++) ABi++; Is following a correct translation LV vB, rB Load indices in B vector LVI vA, rA, vB Gather initial A values ADDV vA, vA, 1 Increment SVI vA, rA, vB Scatter incremented values Joel Emer November 30, 2005 6.823, L2227 Vector Conditional Execution Problem: Want to vectorize loops with conditional code: for (i=0; iN; i++) if (Ai0) then Ai = Bi; Solution: Add vector mask (or flag) registers – vector version of predicate registers, 1 bit per element …and maskable vector instructions – vector operation becomes NOP at elements where mask bit is clear Code example: CVM Turn on all elements LV vA, rA Load entire A vector SGTVS.D vA, F0 Set bits in mask register where A0 LV vA, rB Load B vector into A under mask SV vA, rA Store A back to memory under mask Joel Emer November 30, 2005 6.823, L2228 Masked Vector Instructions Simple Implementation DensityTime Implementation – execute all N operations, turn off result – scan mask vector and only execute writeback according to mask elements with nonzero masks M7=1 A7 B7 M7=1 M6=0 A6 B6 M6=0 A7 B7 M5=1 A5 B5 M5=1 M4=1 A4 B4 M4=1 C5 M3=0 A3 B3 M3=0 M2=0 C4 M1=1 M2=0 C2 M0=0 C1 M1=1 C1 Write data port M0=0 C0 Write Enable Write data port Joel Emer November 30, 2005 6.823, L2229 Compress/Expand Operations • Compress packs nonmasked elements from one vector register contiguously at start of destination vector register – population count of mask vector gives packed vector length • Expand performs inverse operation A7 M7=1 A7 A7 M7=1 A5 M6=0 A6 B6 M6=0 A4 M5=1 A5 A5 M5=1 A1 M4=1 A4 A4 M4=1 M3=0 A3 A7 B3 M3=0 M2=0 A2 A5 B2 M2=0 M1=1 A1 A4 A1 M1=1 M0=0 A0 A1 B0 M0=0 Compress Expand Used for densitytime conditionals and also for general selection operations Joel Emer November 30, 2005 6.823, L2230 Vector Reductions Problem: Loopcarried dependence on reduction variables sum = 0; for (i=0; iN; i++) sum += Ai; Loopcarried dependence on sum Solution: Reassociate operations if possible, use binary tree to perform reduction Rearrange as: sum0:VL1 = 0 Vector of VL partial sums for(i=0; iN; i+=VL) Stripmine VLsized chunks sum0:VL1 += Ai:i+VL1; Vector sum Now have VL partial sums in one vector register do VL = VL/2; Halve vector length sum0:VL1 += sumVL:2VL1 Halve no. of partials while (VL1) Joel Emer November 30, 2005 6.823, L2231 A Modern Vector Super: NEC SX6 (2003) • CMOS Technology – 500 MHz CPU, fits on single chip – SDRAM main memory (up to 64GB) • Scalar unit Image removed due – 4way superscalar with outoforder and speculative to copyright execution restrictions. – 64KB Icache and 64KB data cache Image available in • Vector unit Kitagawa, K., S. – 8 foreground VRegs + 64 background VRegs (256x64 Tagaya, Y. Hagihara, bit elements/VReg) and Y. Kanoh. "A – 1 multiply unit, 1 divide unit, 1 add/shift unit, 1 logical hardware overview of unit, 1 mask unit SX6 and SX7 –8 lanes (8 GFLOPS peak, 16 FLOPS/cycle) supercomputer." NEC Research – 1 load store unit (32x8 byte accesses/cycle) Development Journal – 32 GB/s memory bandwidth per processor 44, no. 1 (Jan • SMP structure 2003):27. – 8 CPUs connected to memory through crossbar – 256 GB/s shared memory bandwidth (4096 interleaved banks) Joel Emer November 30, 2005 6.823, L2232 Multimedia Extensions • Very short vectors added to existing ISAs for micros • Usually 64bit registers split into 2x32b or 4x16b or 8x8b • Newer designs have 128bit registers (Altivec, SSE2) • Limited instruction set: – no vector length control – no strided load/store or scatter/gather – unitstride loads must be aligned to 64/128bit boundary • Limited vector register length: – requires superscalar dispatch to keep multiply/add/load units busy – loop unrolling to hide latencies increases register pressure • Trend towards fuller vector support in microprocessors
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