Multilevel memories in computer architecture

non volatile multilevel memories for digital applications and multi level flash memories
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Dr.ShaneMatts,United States,Teacher
Published Date:23-07-2017
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1 Multilevel Memories Joel Emer Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology Based on the material prepared by Krste Asanovic and Arvind 6.823 L7- 2 Joel Emer CPU-Memory Bottleneck CPU Memory Performance of high-speed computers is usually limited by memory bandwidth & latency • Latency (time for a single access) Memory access time Processor cycle time • Bandwidth (number of accesses per unit time) if fraction m of instructions access memory, ⇒1+m memory references / instruction ⇒ CPI = 1 requires 1+m memory refs / cycle October 3, 2005 6.823 L7- 3 Joel Emer Core Memory • Core memory was first large scale reliable main memory – invented by Forrester in late 40s at MIT for Whirlwind project • Bits stored as magnetization polarity on small ferrite cores threaded onto 2 dimensional grid of wires • Coincident current pulses on X and Y wires would write cell and also sense original state (destructive reads) • Robust, non-volatile storage • Used on space shuttle Image removed due to computers until recently copyright restrictions. • Cores threaded onto wires by hand (25 billion a year at peak production) • Core access time 1µs DEC PDP-8/E Board, 4K words x 12 bits, (1968) October 3, 2005 6.823 L7- 4 Joel Emer Semiconductor Memory, DRAM • Semiconductor memory began to be competitive in early 1970s – Intel formed to exploit market for semiconductor memory • First commercial DRAM was Intel 1103 – 1Kbit of storage on single chip – charge on a capacitor used to hold value • Semiconductor memory quickly replaced core in 1970s October 3, 2005 6.823 L7- 5 Joel Emer One Transistor Dynamic RAM TiN top electrode (V ) REF 1-T DRAM Cell Ta O dielectric 2 5 word Image removed due to copyright restrictions. access FET bit Explicit storage poly W bottom TiN/Ta2O5/W Capacitor capacitor (FET word electrode line gate, trench, access fet stack) October 3, 2005 6.823 L7- 6 Joel Emer Processor-DRAM Gap (latency) µProc 60%/year 1000 CPU “Moore’s Law” Processor-Memory Performance Gap: 100 (grows 50% / year) DRAM 10 7%/year DRAM 1 From David Patterson, UC Berkeley Time Four-issue superscalar could execute 800 instructions during cache miss October 3, 2005 Performance 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 6.823 L7- 7 Joel Emer Little’s Law Throughput (T) = Number in Flight (N) / Latency (L) Misses in CPU Memory flight table Example: - Assume infinite bandwidth memory - 100 cycles / memory reference - 1 + 0.2 memory references / instruction ⇒ Table size = 1.2 100 = 120 entries 120 independent memory operations in flight October 3, 2005 6.823 L7- 8 Joel Emer DRAM Architecture bit lines word lines Col. Col. M 1 2 Row 1 N N Row 2 Memory cell (one bit) M N+M Column Decoder & Sense Amplifiers D Data • Bits stored in 2-dimensional arrays on chip • Modern chips have around 4 logical banks on each chip – each logical bank physically implemented as many smaller arrays October 3, 2005 Row Address Decoder 6.823 L7- 9 Joel Emer DRAM Operation Three steps in read/write access to a given bank • Row access (RAS) – decode row address, enable addressed row (often multiple Kb in row) – bitlines share charge with storage cell – small change in voltage detected by sense amplifiers which latch whole row of bits – sense amplifiers drive bitlines full rail to recharge storage cells • Column access (CAS) – decode column address to select small number of sense amplifier latches (4, 8, 16, or 32 bits depending on DRAM package) – on read, send latched bits out to chip pins – on write, change sense amplifier latches which then charge storage cells to required value – can perform multiple column accesses on same row without another row access (burst mode) • Precharge – charges bit lines to known value, required before next row access Each step has a latency of around 20ns in modern DRAMs Various DRAM standards (DDR, RDRAM) have different ways of encoding the signals for transmission to the DRAM, but all share the same core architecture October 3, 2005 Multilevel Memory Strategy: Hide latency using small, fast memories called caches. Caches are a mechanism to hide memory latency based on the empirical observation that the patterns of memory references made by a processor are often highly predictable: PC … 96 loop: ADD r2, r1, r1 100 What is the pattern of instruction SUBI r3, r3, 1 104 memory addresses? BNEZ r3, loop 108 … 112 October 3, 2005 Typical Memory Reference Patterns Address linear sequence n loop iterations Instruction fetches Stack accesses Data accesses Time October 3, 2005 Common Predictable Patterns Two predictable properties of memory references: – Temporal Locality: If a location is referenced it is likely to be referenced again in the near future. – Spatial Locality: If a location is referenced it is likely that locations near it will be referenced in the near future. October 3, 2005 Caches Caches exploit both types of predictability: – Exploit temporal locality by remembering the contents of recently accessed locations. – Exploit spatial locality by fetching blocks of data around recently accessed locations. October 3, 2005 6.823 L7- 14 Joel Emer Memory Hierarchy Small, A B Big, Slow Fast CPU Memory Memory (DRAM) (RF, SRAM) holds frequently used data • size: Register SRAM DRAM why? • latency: Register SRAM DRAM why? • bandwidth: on-chip off-chip why? On a data access: hit (data ∈ fast memory) ⇒ low latency access miss (data ∉ fast memory) ⇒ long latency access (DRAM) Fast mem. effective only if bandwidth requirement at B A October 3, 2005 6.823 L7- 15 Joel Emer Management of Memory Hierarchy • Small/fast storage, e.g., registers – Address usually specified in instruction – Generally implemented directly as a register file • but hardware might do things behind software’s back, e.g., stack management, register renaming • Large/slower storage, e.g., memory – Address usually computed from values in register – Generally implemented as a cache hierarchy • hardware decides what is kept in fast memory • but software may provide “hints”, e.g., don’t cache or prefetch October 3, 2005 6.823 L7- 16 Joel Emer A Typical Memory Hierarchy c.2003 Split instruction & data Multiple interleaved primary caches memory banks (on-chip SRAM) (DRAM) L1 Memory Instruction Cache CPU Memory Unified L2 Cache Memory L1 Data RF Memory Cache Multiported Large unified secondary cache register file (on-chip SRAM) (part of CPU) October 3, 2005 6.823 L7- 17 Joel Emer Workstation Memory System (Apple PowerMac G5, 2003) Image removed due to copyright restrictions. To view image, visit • Dual 2GHz processors, each with 64KB I- cache, 32KB D-cache, and 512KB L2 unified cache • 1GB/s1GHz, 2x32-bit bus, 16GB/s • North Bridge Chip • Up to 8GB DRAM, 400MHz, 128-bit bus, 6.4GB/s • AGP Graphics Card, 533MHz, 32-bit bus, 2. • PCI-X Expansion, 133MHz, 64-bit bus, 1 GB/s October 3, 2005 18 Five-minute break to stretch your legs Inside a Cache Address Address Main Processor CACHE Memory Data Data copy of main copy of main memory memory location 100 location 101 Data Data Byte Byte 100 Line Data Byte 304 6848 Address Tag Data Block October 3, 2005 Cache Algorithm (Read) Look at Processor Address, search cache tags to find match. Then either Found in cache Not in cache a.k.a. HIT a.k.a. MISS Return copy Read block of data from of data from Main Memory cache Wait … Return data to processor and update cache Q: Which line do we replace? October 3, 2005